Commit Graph

5 Commits

Author SHA1 Message Date
Max Filippov 18da932641 target-xtensa: add DEBUG_SECTION to overlay tool
Fill debug configuration from overlay definitions in the DEBUG_SECTION.
Add DEBUG_SECTION to DC232B and FSF cores.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-20 20:07:12 +04:00
Max Filippov b96ac3e4cc target-xtensa: define TLB_TEMPLATE for MMU-less cores
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18 01:25:27 +04:00
Max Filippov 0fdd2e1d06 target-xtensa: fix MMUv3 initialization
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;
- ITLB/DTLB way 6 attr field is set to 3 on reset.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-26 09:44:34 +00:00
Max Filippov 0c852e171b target-xtensa: handle cache options in the overlay tool
Cache options must be enabled for the cores that have cache to avoid
illegal instruction exceptions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02 05:05:52 +04:00
Max Filippov ac8b7db493 target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks from
data available in the linux architecture variant overlay.

Overlay data is automatically generated in the core configuration
process by Tensilica tools and can be directly converted to qemu xtensa
core description by overlay_tool.h

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16 10:39:52 +00:00