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Author SHA1 Message Date
Tao Xu b0a1980384 i386: Update stepping of Cascadelake-Server 
Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20181227024304.12182-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2019-01-28 15:51:54 -02:00
Peter Maydell 3a183e330d Backend vector enhancements 
Dynamic tlb resizing
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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging

Backend vector enhancements
Dynamic tlb resizing

# gpg: Signature made Mon 28 Jan 2019 15:57:19 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190128: (23 commits)
  cputlb: Remove static tlb sizing
  tcg/tci: enable dynamic TLB sizing
  tcg/mips: enable dynamic TLB sizing
  tcg/mips: Fix tcg_out_qemu_ld_slow_path
  tcg/arm: enable dynamic TLB sizing
  tcg/riscv: enable dynamic TLB sizing
  tcg/s390: enable dynamic TLB sizing
  tcg/sparc: enable dynamic TLB sizing
  tcg/ppc: enable dynamic TLB sizing
  tcg/aarch64: enable dynamic TLB sizing
  tcg/i386: enable dynamic TLB sizing
  tcg: introduce dynamic TLB sizing
  cputlb: do not evict empty entries to the vtlb
  tcg/aarch64: Implement vector minmax arithmetic
  tcg/aarch64: Implement vector saturating arithmetic
  tcg/i386: Implement vector minmax arithmetic
  tcg/i386: Implement vector saturating arithmetic
  tcg/i386: Split subroutines out of tcg_expand_vec_op
  tcg: Add opcodes for vector minmax arithmetic
  tcg: Add opcodes for vector saturated arithmetic
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-28 16:26:47 +00:00
Richard Henderson e77c89fb08 cputlb: Remove static tlb sizing 
Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB,
remove the define and the old code.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:35 -08:00
Richard Henderson 0a9a83d6bf tcg/tci: enable dynamic TLB sizing 
This is automatic due to TCI using the other softtlb macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson ac33373e0e tcg/mips: enable dynamic TLB sizing 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson a31aa4ce00 tcg/mips: Fix tcg_out_qemu_ld_slow_path 
Patch the branch after it has been emitted rather
than before it exists.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson cd7d3cb7a2 tcg/arm: enable dynamic TLB sizing 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson 41b70f220b tcg/riscv: enable dynamic TLB sizing 
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:24 -08:00
Richard Henderson 4f47e338f6 tcg/s390: enable dynamic TLB sizing 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson 17ff9f7801 tcg/sparc: enable dynamic TLB sizing 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson 644f591ab0 tcg/ppc: enable dynamic TLB sizing 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Richard Henderson f7bcd96669 tcg/aarch64: enable dynamic TLB sizing 
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:04:10 -08:00
Emilio G. Cota 54eaf40b8f tcg/i386: enable dynamic TLB sizing 
As the following experiments show, this series is a net perf gain,
particularly for memory-heavy workloads. Experiments are run on an
Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz.

1. System boot + shudown, debian aarch64:

- Before (v3.1.0):
 Performance counter stats for './die.sh v3.1.0' (10 runs):

       9019.797015      task-clock (msec)         #    0.993 CPUs utilized            ( +-  0.23% )
    29,910,312,379      cycles                    #    3.316 GHz                      ( +-  0.14% )
    54,699,252,014      instructions              #    1.83  insn per cycle           ( +-  0.08% )
    10,061,951,686      branches                  # 1115.541 M/sec                    ( +-  0.08% )
       172,966,530      branch-misses             #    1.72% of all branches          ( +-  0.07% )

       9.084039051 seconds time elapsed                                          ( +-  0.23% )

- After:
 Performance counter stats for './die.sh tlb-dyn-v5' (10 runs):

       8624.084842      task-clock (msec)         #    0.993 CPUs utilized            ( +-  0.23% )
    28,556,123,404      cycles                    #    3.311 GHz                      ( +-  0.13% )
    51,755,089,512      instructions              #    1.81  insn per cycle           ( +-  0.05% )
     9,526,513,946      branches                  # 1104.641 M/sec                    ( +-  0.05% )
       166,578,509      branch-misses             #    1.75% of all branches          ( +-  0.19% )

       8.680540350 seconds time elapsed                                          ( +-  0.24% )

That is, a 4.4% perf increase.

2. System boot + shutdown, ubuntu 18.04 x86_64:

- Before (v3.1.0):
      56100.574751      task-clock (msec)         #    1.016 CPUs utilized            ( +-  4.81% )
   200,745,466,128      cycles                    #    3.578 GHz                      ( +-  5.24% )
   431,949,100,608      instructions              #    2.15  insn per cycle           ( +-  5.65% )
    77,502,383,330      branches                  # 1381.490 M/sec                    ( +-  6.18% )
       844,681,191      branch-misses             #    1.09% of all branches          ( +-  3.82% )

      55.221556378 seconds time elapsed                                          ( +-  5.01% )

- After:
      56603.419540      task-clock (msec)         #    1.019 CPUs utilized            ( +- 10.19% )
   202,217,930,479      cycles                    #    3.573 GHz                      ( +- 10.69% )
   439,336,291,626      instructions              #    2.17  insn per cycle           ( +- 14.14% )
    80,538,357,447      branches                  # 1422.853 M/sec                    ( +- 16.09% )
       776,321,622      branch-misses             #    0.96% of all branches          ( +-  3.77% )

      55.549661409 seconds time elapsed                                          ( +- 10.44% )

No improvement (within noise range). Note that for this workload,
increasing the time window too much can lead to perf degradation,
since it flushes the TLB *very* frequently.

3. x86_64 SPEC06int:

           x86_64-softmmu speedup vs. v3.1.0 for SPEC06int (test set)
            Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake)

5.5 +------------------------------------------------------------------------+
    |                   +-+                                                  |
  5 |-+.................+-+...............................tlb-dyn-v5.......+-|
    |                   * *                                                  |
4.5 |-+.................*.*................................................+-|
    |                   * *                                                  |
  4 |-+.................*.*................................................+-|
    |                   * *                                                  |
3.5 |-+.................*.*................................................+-|
    |                   * *                                                  |
  3 |-+......+-+*.......*.*................................................+-|
    |        *  *       * *                                                  |
2.5 |-+......*..*.......*.*.................................+-+*...........+-|
    |        *  *       * *                                 *  *             |
  2 |-+......*..*.......*.*.................................*..*...........+-|
    |        *  *       * *                                 *  *  +-+        |
1.5 |-+......*..*.......*.*.................................*..*.*+-+.*+-+.+-|
    |        *  * *+-+  * *  +-+       *+-+  +-+       +-+  *  * *  * *  *   |
  1 |++++-+*+*++*+*++*++*+*++*+*+++-+*+*+-++*+-++++-++++-+++*++*+*++*+*++*+++|
    |   *  * *  * *  *  * *  * *  *  * *  * *  *  * *  * *  *  * *  * *  *   |
0.5 +------------------------------------------------------------------------+
  400.perlb401.bzip403.g429445.g456.hm462.libq464.h471.omn47483.xalancbgeomean
  png: https://imgur.com/YRF90f7

That is, a 1.51x average speedup over the baseline, with a max speedup
of 5.17x.

Here's a different look at the SPEC06int results, using KVM as the baseline:

             x86_64-softmmu slowdown vs. KVM for SPEC06int (test set)
             Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake)

25 +---------------------------------------------------------------------------+
   |                   +-+                                        +-+          |
   |                   * *                             +-+      v3.1.0         |
   |                   * *                             +-+  tlb-dyn-v5         |
   |                   * *                             * *        +-+          |
20 |-+.................*.*.............................*.+-+......*.*........+-|
   |                   * *                             * # #      * *          |
   |        +-+        * *                             * # #      * *          |
   |        * *        * *                             * # #      * *          |
15 |-+......*.*........*.*.............................*.#.#......*.+-+......+-|
   |        * *        * *                             * # #      * #|#        |
   |        * *        * *        +-+                  * # #      * +-+        |
   |        * *  +-+   * *        ++-+       +-+       * # #      * # # +-+    |
   |        * *  +-+   * *        * ##       *|   +-+  * # #      * # # +-+    |
10 |-+......*.*..*.+-+.*.*........*.##.......++-+.*.+-+*.#.#......*.#.#.*.*..+-|
   |        * *  * +-+ * *        * ## +-+   *# # * # #* # # +-+  * # # * *    |
   |        * *  * # # * *  +-+   * ## * +-+ *# # * # #* # # * *  * # # *+-+   |
   |        * *  * # # * *  * +-+ * ## * # # *# # * # #* # # * *  * # # * ##   |
 5 |-+......*.+-+*.#.#.*.*..*.#.#.*.##.*.#.#.*#.#.*.#.#*.#.#.*.*..*.#.#.*.##.+-|
   |        * # #* # # * +-+* # # * ## * # # *# # * # #* # # * *  * # # * ##   |
   |        * # #* # # * # #* # # * ## * # # *# # * # #* # # * +-+* # # * ##   |
   |   ++-+ * # #* # # * # #* # # * ## * # # *# # * # #* # # * # #* # # * ##   |
   |+++*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+*+#+#+*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+++|
 0 +---------------------------------------------------------------------------+
 400.perlbe401.bzi403.gc429445.go456.h462.libqu464.h471.omne4483.xalancbmgeomean
  png: https://imgur.com/YzAMNEV

After this series, we bring down the average SPEC06int slowdown vs KVM
from 11.47x to 7.58x.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20190116170114.26802-4-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Emilio G. Cota 86e1eff8bc tcg: introduce dynamic TLB sizing 
Disabled in all TCG backends for now.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20190116170114.26802-3-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Emilio G. Cota 3cea94bbc9 cputlb: do not evict empty entries to the vtlb 
Currently we evict an entry to the victim TLB when it doesn't match
the current address. But it could be that there's no match because
the current entry is empty (i.e. all -1's, for instance via tlb_flush).
Do not evict the entry to the vtlb in that case.

This change will help us keep track of the TLB's use rate, which
we'll use to implement a policy for dynamic TLB sizing.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <20190116170114.26802-2-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 93f332a503 tcg/aarch64: Implement vector minmax arithmetic 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson d32648d445 tcg/aarch64: Implement vector saturating arithmetic 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson bc37faf4cb tcg/i386: Implement vector minmax arithmetic 
The avx instruction set does not directly provide MO_64.
We can still implement 64-bit with comparison and vpblendvb.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 8ffafbcec2 tcg/i386: Implement vector saturating arithmetic 
Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 44f1441dbe tcg/i386: Split subroutines out of tcg_expand_vec_op 
This routine was becoming too large.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson dd0a0fcdd8 tcg: Add opcodes for vector minmax arithmetic 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 8afaf05066 tcg: Add opcodes for vector saturated arithmetic 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 5d6acdd4a4 tcg: Add write_aofs to GVecGen4 
This allows writing 2 output, 3 input operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson f550805d83 tcg: Add gvec expanders for nand, nor, eqv 
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Richard Henderson 9a9eda78e4 tcg: Add logical simplifications during gvec expand 
We handle many of these during integer expansion, and the
rest of them during integer optimization.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2019-01-28 07:03:34 -08:00
Peter Maydell 5f39a91dbd Pull request 
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Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging

Pull request

# gpg: Signature made Fri 25 Jan 2019 22:06:08 GMT
# gpg:                using RSA key 7DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* remotes/jnsnow/tags/ide-pull-request:
  ide/via: Implement and use native PCI IDE mode
  ide/via: Rename functions to match device name
  ide/via: Remove vt82c686b_init_ports() function
  sii3112: Remove duplicated code and use PCI IDE ops instead
  ide: Get rid of CMD646BAR struct
  cmd646: Move PCI IDE specific functions to ide/pci.c
  cmd646: Remove IDEBus from CMD646BAR
  cmd646: Remove unused variable

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-28 12:54:06 +00:00
BALATON Zoltan 4ea98d317e ide/via: Implement and use native PCI IDE mode 
This device only implemented ISA compatibility mode and native PCI IDE
mode was missing but no clients actually need ISA mode but to the
contrary, they usually want to switch to and use device in native
PCI IDE mode. Therefore implement native PCI mode and switch default
to that.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-id: c323f08c59b9931310c5d92503d370f77ce3a557.1548160772.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:12 -05:00
BALATON Zoltan 7dd687ba1b ide/via: Rename functions to match device name 
The device is called via-ide and the modelled IDE controller is not
specific to 82C686B but is also usable independently. Therefore, change
function name prefixes accordingly to match device name.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-id: 2905ced862c8d2ad509d73152171ce2472d72605.1548160772.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:12 -05:00
BALATON Zoltan 0252e66c5a ide/via: Remove vt82c686b_init_ports() function 
This function is only called once from vt82c686b_ide_realize() and its
content is simple enough to not need a separate function but be
included in realize directly (as done in other IDE models except PIIX
currently).

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-id: 47d854e0fa41dad6861107eac61327c247965566.1548160772.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
BALATON Zoltan 4eefdf7c1b sii3112: Remove duplicated code and use PCI IDE ops instead 
Parts of the SiI3112 mmio are identical to PCI IDE registers so we can
use the corresponding functions that were factored out into ide/pci.c.
This removes code duplication and simplifies the SiI3112 model which
also helped to spot a copy paste error where reading status of the
2nd channel read the 1st channel instead. This is also fixed here.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 793b6a7934ef2bba26b8d066bec446019efa6c5d.1547166960.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
BALATON Zoltan 8ac98d1a97 ide: Get rid of CMD646BAR struct 
Now that no CMD646 specific parts are left in CMD646BAR (all remaining
members are really PCI IDE specific) this struct can be deleted moving
the memory regions for PCI IDE BARs to PCIIDEState where they better
belong. The CMD646 PCI IDE model is adjusted accordingly.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 4b6cb2ae150dc0d21178209e4beb1e35140a7325.1547166960.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
BALATON Zoltan c9ebc75dc2 cmd646: Move PCI IDE specific functions to ide/pci.c 
The io mem ops callbacks are not specific to CMD646 but really follow
the PCI IDE spec so move these from cmd646.c to pci.c to allow other
PCI IDE implementations to use them.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: a2b1b2b74afdc78330b8b75605687f683a249635.1547166960.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
BALATON Zoltan e210ec87b9 cmd646: Remove IDEBus from CMD646BAR 
The cmd646 io mem ops callbacks only need the IDEBus which is
currently passed via a CMD646BAR struct. No need to wrap it up like
that, we can pass it directly to these callbacks which then allows to
drop the IDEBus from the CMD646BAR.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 7a31c155c9899869794499d841d30c7ef32aae47.1547166960.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
BALATON Zoltan 2ab2ef0785 cmd646: Remove unused variable 
There was a pointer to PCIIDEState in CMD646BAR which was set but
not used afterwards. Get rid of this unused variable.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1e352f091aa601fb2e19771aac46529fe278dd91.1547166960.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
 2019-01-25 14:52:11 -05:00
Peter Maydell ad7a21e812 Python 3 compatibility fixes 
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 =xAEc
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging

Python 3 compatibility fixes

# gpg: Signature made Fri 25 Jan 2019 14:04:56 GMT
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/python-next-pull-request:
  decodetree: re.fullmatch was added in 3.4
  device-crash-test: Python 3 compatibility fix

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 17:22:20 +00:00
Peter Maydell 2dc2f10de3 MIPS queue for January 25, 2019 
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
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 =O/OP
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging

MIPS queue for January 25, 2019

# gpg: Signature made Fri 25 Jan 2019 13:25:57 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-january-25-2019:
  docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models
  qemu-doc: Add nanoMIPS ISA information
  tests: tcg: mips: Remove old directories
  tests: tcg: mips: Add two new Makefiles
  tests: tcg: mips: Move source files to new locations
  MAINTAINERS: Update MIPS sections
  target/mips: Add I6500 core configuration
  target/mips: nanoMIPS: Fix branch handling
  disas: nanoMIPS: Amend DSP instructions related comments
  target/mips: Extend gen_scwp() functionality to support EVA
  target/mips: Correct the second argument type of cpu_supports_isa()
  target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers
  target/mips: nanoMIPS: Remove an unused macro
  target/mips: nanoMIPS: Remove duplicate macro definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 16:31:02 +00:00
Paolo Bonzini 651514df88 decodetree: re.fullmatch was added in 3.4 
Python 3 versions earlier than 3.4 do not have it, use the
same workaround that is in place for 3.0.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1548410602-16008-1-git-send-email-pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2019-01-25 11:41:42 -02:00
Nisarg Shah 55e0a34635 device-crash-test: Python 3 compatibility fix 
Restrict whitelist entry stats in debug mode to be sorted only by
"count", since Python 3 does not implicitly support comparing
dictionaries.

Signed-off-by: Nisarg Shah <nshah@disroot.org>
Message-Id: <20190116183358.30287-1-nshah@disroot.org>
[ehabkost: removed 2 unnecessary hunks from patch]
[ehabkost: edited commit message]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
 2019-01-25 11:41:33 -02:00
Peter Maydell 9dd0d8111f QAPI patches for 2019-01-24 
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 =Oima
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-01-24' into staging

QAPI patches for 2019-01-24

# gpg: Signature made Thu 24 Jan 2019 14:25:19 GMT
# gpg:                using RSA key 3870B400EB918653
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>"
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>"
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-qapi-2019-01-24:
  json: Fix % handling when not interpolating
  qmp: Add examples to qom list, get, and set commands
  qapi: Eliminate indirection through qmp_event_get_func_emit()
  qapi: Belatedly update docs for commit 9c2f56e9f9

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 11:52:12 +00:00
Peter Maydell 87f6a866f1 audio: pc speaker init fix, rework driver probing 
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 =EUbq
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/kraxel/tags/audio-20190124-pull-request' into staging

audio: pc speaker init fix, rework driver probing

# gpg: Signature made Thu 24 Jan 2019 13:19:52 GMT
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/audio-20190124-pull-request:
  audio: probe audio drivers by default
  audio: error message tweak
  audio: check for pulseaudio daemon pidfile
  audio: use try-sdl for openbsd
  audio: allow optional audio drivers.
  audio: use pkg-config
  audio: fix pc speaker init

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 10:38:03 +00:00
Vladimir Sementsov-Ogievskiy ff12e3ae3d trace: improve runstate tracing 
Trace previous state, move tracepoint to runstate_set start (to cover
all cases for debugging), add string representations of traced states.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-id: 20190124125154.474650-1-vsementsov@virtuozzo.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
 2019-01-25 10:21:27 +00:00
Peter Maydell 7d8df3272d - Some typo and UTF-8 fixes 
- a ppc e6500 fix to remove duplicate SPR registering
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Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging

- Some typo and UTF-8 fixes
- a ppc e6500 fix to remove duplicate SPR registering

# gpg: Signature made Thu 24 Jan 2019 12:48:05 GMT
# gpg:                using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-patches-pull-request:
  hw/i386/pc.c: fix one typo in function name
  virtio-net: Fix a typo
  ppc: e6500 registers SPR 604 twice
  contrib/gitdm: Fix a typo
  MAINTAINERS: Fix utf-8 mangling

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 09:54:47 +00:00
Peter Maydell feff020891 Merge qio 2010/01/24 
Fixes accidental deletion of VNC server UNIX listener socket
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 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/berrange/tags/qio-next-pull-request' into staging

Merge qio 2010/01/24

Fixes accidental deletion of VNC server UNIX listener socket

# gpg: Signature made Thu 24 Jan 2019 12:24:43 GMT
# gpg:                using RSA key BE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>"
# gpg:                 aka "Daniel P. Berrange <berrange@redhat.com>"
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E  8E3F BE86 EBB4 1510 4FDF

* remotes/berrange/tags/qio-next-pull-request:
  io: ensure UNIX client doesn't unlink server socket

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 2019-01-25 09:26:33 +00:00
Stefan Markovic e5a5b1bb7c docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models 
Add list of supported and preferred CPU models for MIPS32, MIPS64
and nanoMIPS hosts.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Stefan Markovic f7d257cb4a qemu-doc: Add nanoMIPS ISA information 
Add nanoMIPS information in qemu-doc.texi. An example of usage
is included.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Aleksandar Markovic dcca150f83 tests: tcg: mips: Remove old directories 
Remove old test directories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Aleksandar Markovic 5e0aa63b08 tests: tcg: mips: Add two new Makefiles 
Add Makefiles for two new direcitories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Aleksandar Markovic 073d9f2ce0 tests: tcg: mips: Move source files to new locations 
MIPS TCG test will be organized by ISAs and ASEs in future.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Aleksandar Markovic b304981f52 MAINTAINERS: Update MIPS sections 
Remove Stefan Markovic as a reviewer for MIPS directories and
files, as he left Wave Computing.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00
Yongbok Kim ca1ffd14ed target/mips: Add I6500 core configuration 
Add I6500 core configuration. Note that this configuration is
supported only on best-effort basis due to the lack of certain
features in QEMU.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
 2019-01-24 17:48:33 +01:00