mirror of https://gitee.com/openkylin/qemu.git
147 lines
4.0 KiB
C
147 lines
4.0 KiB
C
/*
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* SuperH gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
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/* FIXME: We should use XML for this. */
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int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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CPUSH4State *env = &cpu->env;
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switch (n) {
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case 0 ... 7:
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if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) {
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return gdb_get_regl(mem_buf, env->gregs[n + 16]);
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} else {
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return gdb_get_regl(mem_buf, env->gregs[n]);
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}
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case 8 ... 15:
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return gdb_get_regl(mem_buf, env->gregs[n]);
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case 16:
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return gdb_get_regl(mem_buf, env->pc);
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case 17:
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return gdb_get_regl(mem_buf, env->pr);
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case 18:
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return gdb_get_regl(mem_buf, env->gbr);
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case 19:
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return gdb_get_regl(mem_buf, env->vbr);
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case 20:
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return gdb_get_regl(mem_buf, env->mach);
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case 21:
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return gdb_get_regl(mem_buf, env->macl);
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case 22:
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return gdb_get_regl(mem_buf, cpu_read_sr(env));
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case 23:
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return gdb_get_regl(mem_buf, env->fpul);
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case 24:
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return gdb_get_regl(mem_buf, env->fpscr);
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case 25 ... 40:
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if (env->fpscr & FPSCR_FR) {
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stfl_p(mem_buf, env->fregs[n - 9]);
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} else {
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stfl_p(mem_buf, env->fregs[n - 25]);
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}
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return 4;
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case 41:
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return gdb_get_regl(mem_buf, env->ssr);
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case 42:
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return gdb_get_regl(mem_buf, env->spc);
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case 43 ... 50:
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return gdb_get_regl(mem_buf, env->gregs[n - 43]);
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case 51 ... 58:
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return gdb_get_regl(mem_buf, env->gregs[n - (51 - 16)]);
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}
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return 0;
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}
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int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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SuperHCPU *cpu = SUPERH_CPU(cs);
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CPUSH4State *env = &cpu->env;
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switch (n) {
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case 0 ... 7:
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if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) {
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env->gregs[n + 16] = ldl_p(mem_buf);
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} else {
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env->gregs[n] = ldl_p(mem_buf);
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}
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break;
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case 8 ... 15:
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env->gregs[n] = ldl_p(mem_buf);
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break;
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case 16:
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env->pc = ldl_p(mem_buf);
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break;
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case 17:
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env->pr = ldl_p(mem_buf);
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break;
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case 18:
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env->gbr = ldl_p(mem_buf);
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break;
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case 19:
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env->vbr = ldl_p(mem_buf);
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break;
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case 20:
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env->mach = ldl_p(mem_buf);
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break;
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case 21:
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env->macl = ldl_p(mem_buf);
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break;
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case 22:
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cpu_write_sr(env, ldl_p(mem_buf));
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break;
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case 23:
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env->fpul = ldl_p(mem_buf);
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break;
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case 24:
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env->fpscr = ldl_p(mem_buf);
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break;
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case 25 ... 40:
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if (env->fpscr & FPSCR_FR) {
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env->fregs[n - 9] = ldfl_p(mem_buf);
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} else {
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env->fregs[n - 25] = ldfl_p(mem_buf);
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}
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break;
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case 41:
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env->ssr = ldl_p(mem_buf);
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break;
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case 42:
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env->spc = ldl_p(mem_buf);
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break;
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case 43 ... 50:
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env->gregs[n - 43] = ldl_p(mem_buf);
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break;
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case 51 ... 58:
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env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
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break;
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default:
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return 0;
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}
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return 4;
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}
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