mirror of https://gitee.com/openkylin/qemu.git
439 lines
13 KiB
C
439 lines
13 KiB
C
/*
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* S/390 helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/gdbstub.h"
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#include "qemu/timer.h"
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#include "qemu/qemu-print.h"
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#include "hw/s390x/ioinst.h"
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#include "hw/s390x/pv.h"
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#include "sysemu/hw_accel.h"
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#include "sysemu/runstate.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/tcg.h"
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#endif
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#ifndef CONFIG_USER_ONLY
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void s390x_tod_timer(void *opaque)
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{
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cpu_inject_clock_comparator((S390CPU *) opaque);
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}
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void s390x_cpu_timer(void *opaque)
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{
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cpu_inject_cpu_timer((S390CPU *) opaque);
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}
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong raddr;
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int prot;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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uint64_t tec;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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/* We want to read the code (e.g., see what we are single-stepping).*/
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if (asc != PSW_ASC_HOME) {
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asc = PSW_ASC_PRIMARY;
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}
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/*
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* We want to read code even if IEP is active. Use MMU_DATA_LOAD instead
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* of MMU_INST_FETCH.
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*/
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if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, &tec)) {
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return -1;
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}
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return raddr;
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}
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hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
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{
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hwaddr phys_addr;
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target_ulong page;
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page = vaddr & TARGET_PAGE_MASK;
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phys_addr = cpu_get_phys_page_debug(cs, page);
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phys_addr += (vaddr & ~TARGET_PAGE_MASK);
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return phys_addr;
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}
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static inline bool is_special_wait_psw(uint64_t psw_addr)
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{
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/* signal quiesce */
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return (psw_addr & 0xfffUL) == 0xfffUL;
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}
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void s390_handle_wait(S390CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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if (s390_cpu_halt(cpu) == 0) {
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if (is_special_wait_psw(cpu->env.psw.addr)) {
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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} else {
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cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT;
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qemu_system_guest_panicked(cpu_get_crash_info(cs));
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}
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}
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}
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void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
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{
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uint64_t old_mask = env->psw.mask;
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env->psw.addr = addr;
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env->psw.mask = mask;
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/* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */
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if (!tcg_enabled()) {
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return;
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}
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env->cc_op = (mask >> 44) & 3;
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if ((old_mask ^ mask) & PSW_MASK_PER) {
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s390_cpu_recompute_watchpoints(env_cpu(env));
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}
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if (mask & PSW_MASK_WAIT) {
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s390_handle_wait(env_archcpu(env));
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}
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}
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uint64_t get_psw_mask(CPUS390XState *env)
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{
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uint64_t r = env->psw.mask;
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if (tcg_enabled()) {
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env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
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env->cc_vr);
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r &= ~PSW_MASK_CC;
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assert(!(env->cc_op & ~3));
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r |= (uint64_t)env->cc_op << 44;
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}
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return r;
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}
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LowCore *cpu_map_lowcore(CPUS390XState *env)
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{
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LowCore *lowcore;
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hwaddr len = sizeof(LowCore);
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lowcore = cpu_physical_memory_map(env->psa, &len, true);
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if (len < sizeof(LowCore)) {
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cpu_abort(env_cpu(env), "Could not map lowcore\n");
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}
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return lowcore;
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}
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void cpu_unmap_lowcore(LowCore *lowcore)
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{
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cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
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}
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void do_restart_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->restart_new_psw.mask);
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addr = be64_to_cpu(lowcore->restart_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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env->pending_int &= ~INTERRUPT_RESTART;
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load_psw(env, mask, addr);
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}
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void s390_cpu_recompute_watchpoints(CPUState *cs)
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{
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const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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/* We are called when the watchpoints have changed. First
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remove them all. */
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cpu_watchpoint_remove_all(cs, BP_CPU);
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/* Return if PER is not enabled */
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if (!(env->psw.mask & PSW_MASK_PER)) {
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return;
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}
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/* Return if storage-alteration event is not enabled. */
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if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
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return;
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}
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if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
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/* We can't create a watchoint spanning the whole memory range, so
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split it in two parts. */
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cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
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cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
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} else if (env->cregs[10] > env->cregs[11]) {
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/* The address range loops, create two watchpoints. */
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cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
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wp_flags, NULL);
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cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
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} else {
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/* Default case, create a single watchpoint. */
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cpu_watchpoint_insert(cs, env->cregs[10],
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env->cregs[11] - env->cregs[10] + 1,
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wp_flags, NULL);
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}
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}
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typedef struct SigpSaveArea {
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uint64_t fprs[16]; /* 0x0000 */
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uint64_t grs[16]; /* 0x0080 */
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PSW psw; /* 0x0100 */
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uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */
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uint32_t prefix; /* 0x0118 */
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uint32_t fpc; /* 0x011c */
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uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */
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uint32_t todpr; /* 0x0124 */
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uint64_t cputm; /* 0x0128 */
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uint64_t ckc; /* 0x0130 */
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uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */
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uint32_t ars[16]; /* 0x0140 */
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uint64_t crs[16]; /* 0x0384 */
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} SigpSaveArea;
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QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512);
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int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch)
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{
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static const uint8_t ar_id = 1;
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SigpSaveArea *sa;
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hwaddr len = sizeof(*sa);
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int i;
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/* For PVMs storing will occur when this cpu enters SIE again */
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if (s390_is_pv()) {
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return 0;
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}
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sa = cpu_physical_memory_map(addr, &len, true);
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if (!sa) {
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return -EFAULT;
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}
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if (len != sizeof(*sa)) {
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cpu_physical_memory_unmap(sa, len, 1, 0);
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return -EFAULT;
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}
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if (store_arch) {
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cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1);
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}
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for (i = 0; i < 16; ++i) {
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sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i));
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}
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for (i = 0; i < 16; ++i) {
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sa->grs[i] = cpu_to_be64(cpu->env.regs[i]);
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}
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sa->psw.addr = cpu_to_be64(cpu->env.psw.addr);
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sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env));
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sa->prefix = cpu_to_be32(cpu->env.psa);
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sa->fpc = cpu_to_be32(cpu->env.fpc);
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sa->todpr = cpu_to_be32(cpu->env.todpr);
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sa->cputm = cpu_to_be64(cpu->env.cputm);
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sa->ckc = cpu_to_be64(cpu->env.ckc >> 8);
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for (i = 0; i < 16; ++i) {
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sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]);
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}
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for (i = 0; i < 16; ++i) {
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sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]);
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}
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cpu_physical_memory_unmap(sa, len, 1, len);
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return 0;
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}
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typedef struct SigpAdtlSaveArea {
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uint64_t vregs[32][2]; /* 0x0000 */
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uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */
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uint64_t gscb[4]; /* 0x0400 */
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uint8_t pad_0x0420[0x1000 - 0x0420]; /* 0x0420 */
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} SigpAdtlSaveArea;
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QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096);
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#define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */
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int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len)
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{
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SigpAdtlSaveArea *sa;
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hwaddr save = len;
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int i;
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sa = cpu_physical_memory_map(addr, &save, true);
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if (!sa) {
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return -EFAULT;
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}
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if (save != len) {
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cpu_physical_memory_unmap(sa, len, 1, 0);
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return -EFAULT;
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}
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if (s390_has_feat(S390_FEAT_VECTOR)) {
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for (i = 0; i < 32; i++) {
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sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]);
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sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]);
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}
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}
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if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) {
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for (i = 0; i < 4; i++) {
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sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]);
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}
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}
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cpu_physical_memory_unmap(sa, len, 1, len);
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return 0;
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}
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#endif /* CONFIG_USER_ONLY */
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void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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int i;
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if (env->cc_op > 3) {
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qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
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env->psw.mask, env->psw.addr, cc_name(env->cc_op));
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} else {
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qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
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env->psw.mask, env->psw.addr, env->cc_op);
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}
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for (i = 0; i < 16; i++) {
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qemu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
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if ((i % 4) == 3) {
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qemu_fprintf(f, "\n");
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} else {
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qemu_fprintf(f, " ");
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}
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}
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if (flags & CPU_DUMP_FPU) {
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if (s390_has_feat(S390_FEAT_VECTOR)) {
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c",
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i, env->vregs[i][0], env->vregs[i][1],
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i % 2 ? '\n' : ' ');
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}
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} else {
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for (i = 0; i < 16; i++) {
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qemu_fprintf(f, "F%02d=%016" PRIx64 "%c",
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i, *get_freg(env, i),
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(i % 4) == 3 ? '\n' : ' ');
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}
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}
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}
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < 16; i++) {
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qemu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
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if ((i % 4) == 3) {
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qemu_fprintf(f, "\n");
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} else {
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qemu_fprintf(f, " ");
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}
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}
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#endif
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#ifdef DEBUG_INLINE_BRANCHES
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for (i = 0; i < CC_OP_MAX; i++) {
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qemu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
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inline_branch_miss[i], inline_branch_hit[i]);
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}
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#endif
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qemu_fprintf(f, "\n");
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}
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const char *cc_name(enum cc_op cc_op)
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{
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static const char * const cc_names[] = {
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[CC_OP_CONST0] = "CC_OP_CONST0",
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[CC_OP_CONST1] = "CC_OP_CONST1",
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[CC_OP_CONST2] = "CC_OP_CONST2",
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[CC_OP_CONST3] = "CC_OP_CONST3",
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[CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
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[CC_OP_STATIC] = "CC_OP_STATIC",
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[CC_OP_NZ] = "CC_OP_NZ",
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[CC_OP_LTGT_32] = "CC_OP_LTGT_32",
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[CC_OP_LTGT_64] = "CC_OP_LTGT_64",
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[CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
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[CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
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[CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
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[CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
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[CC_OP_ADD_64] = "CC_OP_ADD_64",
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[CC_OP_ADDU_64] = "CC_OP_ADDU_64",
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[CC_OP_ADDC_64] = "CC_OP_ADDC_64",
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[CC_OP_SUB_64] = "CC_OP_SUB_64",
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[CC_OP_SUBU_64] = "CC_OP_SUBU_64",
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[CC_OP_SUBB_64] = "CC_OP_SUBB_64",
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[CC_OP_ABS_64] = "CC_OP_ABS_64",
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[CC_OP_NABS_64] = "CC_OP_NABS_64",
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[CC_OP_ADD_32] = "CC_OP_ADD_32",
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[CC_OP_ADDU_32] = "CC_OP_ADDU_32",
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[CC_OP_ADDC_32] = "CC_OP_ADDC_32",
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[CC_OP_SUB_32] = "CC_OP_SUB_32",
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[CC_OP_SUBU_32] = "CC_OP_SUBU_32",
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[CC_OP_SUBB_32] = "CC_OP_SUBB_32",
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[CC_OP_ABS_32] = "CC_OP_ABS_32",
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[CC_OP_NABS_32] = "CC_OP_NABS_32",
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[CC_OP_COMP_32] = "CC_OP_COMP_32",
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[CC_OP_COMP_64] = "CC_OP_COMP_64",
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[CC_OP_TM_32] = "CC_OP_TM_32",
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[CC_OP_TM_64] = "CC_OP_TM_64",
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[CC_OP_NZ_F32] = "CC_OP_NZ_F32",
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[CC_OP_NZ_F64] = "CC_OP_NZ_F64",
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[CC_OP_NZ_F128] = "CC_OP_NZ_F128",
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[CC_OP_ICM] = "CC_OP_ICM",
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[CC_OP_SLA_32] = "CC_OP_SLA_32",
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[CC_OP_SLA_64] = "CC_OP_SLA_64",
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[CC_OP_FLOGR] = "CC_OP_FLOGR",
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[CC_OP_LCBB] = "CC_OP_LCBB",
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[CC_OP_VC] = "CC_OP_VC",
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[CC_OP_MULS_32] = "CC_OP_MULS_32",
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[CC_OP_MULS_64] = "CC_OP_MULS_64",
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};
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return cc_names[cc_op];
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}
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