mirror of https://gitee.com/openkylin/qemu.git
208 lines
6.6 KiB
C
208 lines
6.6 KiB
C
/*
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* QEMU Sun4m System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t08.h"
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#define KERNEL_LOAD_ADDR 0x00004000
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#define INITRD_LOAD_ADDR 0x00800000
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#define PROM_ADDR 0xffd00000
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#define PROM_FILENAMEB "proll.bin"
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#define PROM_FILENAMEE "proll.elf"
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#define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
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#define PHYS_JJ_IDPROM_OFF 0x1FD8
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#define PHYS_JJ_EEPROM_SIZE 0x2000
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// IRQs are not PIL ones, but master interrupt controller register
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// bits
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#define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
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#define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */
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#define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */
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#define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
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#define PHYS_JJ_LE_IRQ 16
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#define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
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#define PHYS_JJ_CLOCK_IRQ 7
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#define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
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#define PHYS_JJ_CLOCK1_IRQ 19
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#define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
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#define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
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#define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
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#define PHYS_JJ_MS_KBD_IRQ 14
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#define PHYS_JJ_SER 0x71100000 /* Serial */
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#define PHYS_JJ_SER_IRQ 15
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#define PHYS_JJ_SCSI_IRQ 18
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#define PHYS_JJ_FDC 0x71400000 /* Floppy */
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#define PHYS_JJ_FLOPPY_IRQ 22
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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return qemu_get_clock(vm_clock);
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}
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void DMA_run() {}
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static m48t08_t *nvram;
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static void nvram_init(m48t08_t *nvram, uint8_t *macaddr)
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{
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unsigned char tmp = 0;
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int i, j;
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i = 0x1fd8;
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m48t08_write(nvram, i++, 0x01);
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m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
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j = 0;
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m48t08_write(nvram, i++, macaddr[j++]);
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m48t08_write(nvram, i++, macaddr[j++]);
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m48t08_write(nvram, i++, macaddr[j++]);
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m48t08_write(nvram, i++, macaddr[j++]);
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m48t08_write(nvram, i++, macaddr[j++]);
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m48t08_write(nvram, i, macaddr[j]);
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/* Calculate checksum */
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for (i = 0x1fd8; i < 0x1fe7; i++) {
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tmp ^= m48t08_read(nvram, i);
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}
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m48t08_write(nvram, 0x1fe7, tmp);
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}
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static void *slavio_intctl;
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void pic_info()
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{
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slavio_pic_info(slavio_intctl);
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}
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void irq_info()
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{
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slavio_irq_info(slavio_intctl);
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}
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void pic_set_irq(int irq, int level)
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{
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slavio_pic_set_irq(slavio_intctl, irq, level);
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}
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static void *tcx;
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void vga_update_display()
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{
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tcx_update_display(tcx);
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}
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void vga_invalidate_display()
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{
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tcx_invalidate_display(tcx);
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}
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void vga_screen_dump(const char *filename)
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{
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tcx_screen_dump(tcx, filename);
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}
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static void *iommu;
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uint32_t iommu_translate(uint32_t addr)
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{
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return iommu_translate_local(iommu, addr);
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}
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/* Sun4m hardware initialisation */
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void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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int ret, linux_boot;
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unsigned int i;
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unsigned long vram_size = 0x100000, prom_offset, initrd_size;
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linux_boot = (kernel_filename != NULL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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iommu = iommu_init(PHYS_JJ_IOMMU);
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slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
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tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size);
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lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
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nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr);
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slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
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slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
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slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]);
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fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
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prom_offset = ram_size + vram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
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ret = load_elf(buf, phys_ram_base + prom_offset);
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if (ret < 0) {
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
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ret = load_image(buf, phys_ram_base + prom_offset);
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}
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (linux_boot) {
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ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (ret < 0)
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ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (ret < 0)
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ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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== 0x48647253) { // HdrS
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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}
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}
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}
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}
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}
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