mirror of https://gitee.com/openkylin/qemu.git
582 lines
15 KiB
C
582 lines
15 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "hw/hw.h"
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#include "trace.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/xics.h"
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/*
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* ICP: Presentation layer
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*/
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struct icp_server_state {
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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};
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(ss) (((ss)->xirr) & XISR_MASK)
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#define CPPR(ss) (((ss)->xirr) >> 24)
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struct ics_state;
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struct icp_state {
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long nr_servers;
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struct icp_server_state *ss;
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struct ics_state *ics;
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};
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static void ics_reject(struct ics_state *ics, int nr);
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static void ics_resend(struct ics_state *ics);
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static void ics_eoi(struct ics_state *ics, int nr);
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static void icp_check_ipi(struct icp_state *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
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return;
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}
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trace_xics_icp_check_ipi(server, ss->mfrr);
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
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ss->pending_priority = ss->mfrr;
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qemu_irq_raise(ss->output);
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}
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static void icp_resend(struct icp_state *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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if (ss->mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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}
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ics_resend(icp->ics);
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}
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static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
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{
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struct icp_server_state *ss = icp->ss + server;
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uint8_t old_cppr;
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uint32_t old_xisr;
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old_cppr = CPPR(ss);
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
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if (cppr < old_cppr) {
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if (XISR(ss) && (cppr <= ss->pending_priority)) {
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old_xisr = XISR(ss);
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ss->xirr &= ~XISR_MASK; /* Clear XISR */
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qemu_irq_lower(ss->output);
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ics_reject(icp->ics, old_xisr);
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}
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} else {
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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}
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static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
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{
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struct icp_server_state *ss = icp->ss + server;
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ss->mfrr = mfrr;
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if (mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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}
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}
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static uint32_t icp_accept(struct icp_server_state *ss)
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{
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uint32_t xirr = ss->xirr;
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qemu_irq_lower(ss->output);
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ss->xirr = ss->pending_priority << 24;
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trace_xics_icp_accept(xirr, ss->xirr);
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return xirr;
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}
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static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
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{
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struct icp_server_state *ss = icp->ss + server;
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/* Send EOI -> ICS */
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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trace_xics_icp_eoi(server, xirr, ss->xirr);
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ics_eoi(icp->ics, xirr & XISR_MASK);
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
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{
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struct icp_server_state *ss = icp->ss + server;
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trace_xics_icp_irq(server, nr, priority);
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if ((priority >= CPPR(ss))
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|| (XISR(ss) && (ss->pending_priority <= priority))) {
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ics_reject(icp->ics, nr);
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} else {
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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ss->pending_priority = priority;
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trace_xics_icp_raise(ss->xirr, ss->pending_priority);
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qemu_irq_raise(ss->output);
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}
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}
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/*
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* ICS: Source layer
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*/
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struct ics_irq_state {
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int server;
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uint8_t priority;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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uint8_t status;
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};
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struct ics_state {
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int nr_irqs;
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int offset;
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qemu_irq *qirqs;
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bool *islsi;
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struct ics_irq_state *irqs;
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struct icp_state *icp;
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};
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static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
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{
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return (nr >= ics->offset)
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&& (nr < (ics->offset + ics->nr_irqs));
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}
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static void resend_msi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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/* FIXME: filter by server#? */
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if (irq->status & XICS_STATUS_REJECTED) {
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irq->status &= ~XICS_STATUS_REJECTED;
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if (irq->priority != 0xff) {
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icp_irq(ics->icp, irq->server, srcno + ics->offset,
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irq->priority);
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}
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}
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}
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static void resend_lsi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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if ((irq->priority != 0xff)
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&& (irq->status & XICS_STATUS_ASSERTED)
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&& !(irq->status & XICS_STATUS_SENT)) {
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irq->status |= XICS_STATUS_SENT;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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static void set_irq_msi(struct ics_state *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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trace_xics_set_irq_msi(srcno, srcno + ics->offset);
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if (val) {
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if (irq->priority == 0xff) {
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irq->status |= XICS_STATUS_MASKED_PENDING;
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trace_xics_masked_pending();
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} else {
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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}
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static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
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if (val) {
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irq->status |= XICS_STATUS_ASSERTED;
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} else {
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irq->status &= ~XICS_STATUS_ASSERTED;
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}
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resend_lsi(ics, srcno);
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}
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static void ics_set_irq(void *opaque, int srcno, int val)
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{
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struct ics_state *ics = (struct ics_state *)opaque;
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if (ics->islsi[srcno]) {
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set_irq_lsi(ics, srcno, val);
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} else {
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set_irq_msi(ics, srcno, val);
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}
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}
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static void write_xive_msi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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if (!(irq->status & XICS_STATUS_MASKED_PENDING)
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|| (irq->priority == 0xff)) {
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return;
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}
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irq->status &= ~XICS_STATUS_MASKED_PENDING;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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static void write_xive_lsi(struct ics_state *ics, int srcno)
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{
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resend_lsi(ics, srcno);
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}
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static void ics_write_xive(struct ics_state *ics, int nr, int server,
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uint8_t priority, uint8_t saved_priority)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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irq->server = server;
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irq->priority = priority;
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irq->saved_priority = saved_priority;
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trace_xics_ics_write_xive(nr, srcno, server, priority);
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if (ics->islsi[srcno]) {
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write_xive_lsi(ics, srcno);
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} else {
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write_xive_msi(ics, srcno);
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}
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}
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static void ics_reject(struct ics_state *ics, int nr)
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{
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struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
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trace_xics_ics_reject(nr, nr - ics->offset);
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irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
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irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
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}
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static void ics_resend(struct ics_state *ics)
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{
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int i;
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for (i = 0; i < ics->nr_irqs; i++) {
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/* FIXME: filter by server#? */
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if (ics->islsi[i]) {
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resend_lsi(ics, i);
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} else {
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resend_msi(ics, i);
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}
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}
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}
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static void ics_eoi(struct ics_state *ics, int nr)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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trace_xics_ics_eoi(nr);
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if (ics->islsi[srcno]) {
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irq->status &= ~XICS_STATUS_SENT;
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}
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}
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/*
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* Exported functions
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*/
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qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
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{
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if (!ics_valid_irq(icp->ics, irq)) {
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return NULL;
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}
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return icp->ics->qirqs[irq - icp->ics->offset];
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}
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void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
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{
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assert(ics_valid_irq(icp->ics, irq));
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icp->ics->islsi[irq - icp->ics->offset] = lsi;
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}
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static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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target_ulong cppr = args[0];
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icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
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return H_SUCCESS;
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}
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static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong server = args[0];
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target_ulong mfrr = args[1];
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if (server >= spapr->icp->nr_servers) {
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return H_PARAMETER;
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}
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icp_set_mfrr(spapr->icp, server, mfrr);
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return H_SUCCESS;
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}
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static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
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args[0] = xirr;
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return H_SUCCESS;
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}
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static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUState *cs = CPU(cpu);
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target_ulong xirr = args[0];
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icp_eoi(spapr->icp, cs->cpu_index, xirr);
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return H_SUCCESS;
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}
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static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr, server, priority;
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if ((nargs != 3) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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server = rtas_ld(args, 1);
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priority = rtas_ld(args, 2);
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if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
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|| (priority > 0xff)) {
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rtas_st(rets, 0, -3);
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return;
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}
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ics_write_xive(ics, nr, server, priority, priority);
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rtas_st(rets, 0, 0); /* Success */
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}
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static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 3)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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rtas_st(rets, 0, 0); /* Success */
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rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
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rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
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}
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static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
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ics->irqs[nr - ics->offset].priority);
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rtas_st(rets, 0, 0); /* Success */
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}
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static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
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ics->irqs[nr - ics->offset].saved_priority,
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ics->irqs[nr - ics->offset].saved_priority);
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rtas_st(rets, 0, 0); /* Success */
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}
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static void xics_reset(void *opaque)
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{
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struct icp_state *icp = (struct icp_state *)opaque;
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|
struct ics_state *ics = icp->ics;
|
|
int i;
|
|
|
|
for (i = 0; i < icp->nr_servers; i++) {
|
|
icp->ss[i].xirr = 0;
|
|
icp->ss[i].pending_priority = 0xff;
|
|
icp->ss[i].mfrr = 0xff;
|
|
/* Make all outputs are deasserted */
|
|
qemu_set_irq(icp->ss[i].output, 0);
|
|
}
|
|
|
|
memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs);
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
ics->irqs[i].priority = 0xff;
|
|
ics->irqs[i].saved_priority = 0xff;
|
|
}
|
|
}
|
|
|
|
void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUPPCState *env = &cpu->env;
|
|
struct icp_server_state *ss = &icp->ss[cs->cpu_index];
|
|
|
|
assert(cs->cpu_index < icp->nr_servers);
|
|
|
|
switch (PPC_INPUT(env)) {
|
|
case PPC_FLAGS_INPUT_POWER7:
|
|
ss->output = env->irq_inputs[POWER7_INPUT_INT];
|
|
break;
|
|
|
|
case PPC_FLAGS_INPUT_970:
|
|
ss->output = env->irq_inputs[PPC970_INPUT_INT];
|
|
break;
|
|
|
|
default:
|
|
fprintf(stderr, "XICS interrupt controller does not support this CPU "
|
|
"bus model\n");
|
|
abort();
|
|
}
|
|
}
|
|
|
|
struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
|
|
{
|
|
struct icp_state *icp;
|
|
struct ics_state *ics;
|
|
|
|
icp = g_malloc0(sizeof(*icp));
|
|
icp->nr_servers = nr_servers;
|
|
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
|
|
|
|
ics = g_malloc0(sizeof(*ics));
|
|
ics->nr_irqs = nr_irqs;
|
|
ics->offset = XICS_IRQ_BASE;
|
|
ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
|
|
ics->islsi = g_malloc0(nr_irqs * sizeof(bool));
|
|
|
|
icp->ics = ics;
|
|
ics->icp = icp;
|
|
|
|
ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
|
|
|
|
spapr_register_hypercall(H_CPPR, h_cppr);
|
|
spapr_register_hypercall(H_IPI, h_ipi);
|
|
spapr_register_hypercall(H_XIRR, h_xirr);
|
|
spapr_register_hypercall(H_EOI, h_eoi);
|
|
|
|
spapr_rtas_register("ibm,set-xive", rtas_set_xive);
|
|
spapr_rtas_register("ibm,get-xive", rtas_get_xive);
|
|
spapr_rtas_register("ibm,int-off", rtas_int_off);
|
|
spapr_rtas_register("ibm,int-on", rtas_int_on);
|
|
|
|
qemu_register_reset(xics_reset, icp);
|
|
|
|
return icp;
|
|
}
|