Luc MICHEL 95e9a242e2 target/arm: add data cache invalidation cp15 instruction to cortex-r5 ... The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the data cache on the cortex-r5. Implementing it as a NOP. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2017-06-04 18:42:55 +03:00
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alpha	migration: Remove unneeded includes of migration/vmstate.h	2017-06-01 18:49:22 +02:00
arm	target/arm: add data cache invalidation cp15 instruction to cortex-r5	2017-06-04 18:42:55 +03:00
cris	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
hppa	migration: Remove unneeded includes of migration/vmstate.h	2017-06-01 18:49:22 +02:00
i386	shutdown: Add source information to SHUTDOWN and RESET	2017-05-23 13:28:17 +02:00
lm32	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
m68k	This is the same as the v3 posted except a re-base and a few extra signoffs	2017-01-16 18:23:02 +00:00
microblaze	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
mips	target/mips: fix delay slot detection in gen_msa_branch()	2017-03-20 11:19:14 +00:00
moxie	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
nios2	target/nios2: take BQL around interrupt check	2017-03-14 13:26:37 +01:00
openrisc	target/openrisc: Support non-busy idle state using PMR SPR	2017-05-04 09:39:14 +09:00
ppc	target/ppc: reset reservation in do_rfi()	2017-05-24 11:39:52 +10:00
s390x	migration: Remove unneeded includes of migration/vmstate.h	2017-06-01 18:49:22 +02:00
sh4	target/sh4: fix RTE instruction delay slot	2017-05-30 21:00:56 +02:00
sparc	shutdown: Add source information to SHUTDOWN and RESET	2017-05-23 13:28:17 +02:00
tilegx	migration: Remove unneeded includes of migration/vmstate.h	2017-06-01 18:49:22 +02:00
tricore	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
unicore32	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
xtensa	target/xtensa fixes for 2.9:	2017-03-18 17:24:49 +00:00