mirror of https://gitee.com/openkylin/qemu.git
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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* Nuvoton NPCM7xx Timer Controller
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_TIMER_H
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#define NPCM7XX_TIMER_H
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#include "exec/memory.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
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#define NPCM7XX_TIMERS_PER_CTRL (5)
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
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/* The basic watchdog timer period is 2^14 clock cycles. */
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#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
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#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
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typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
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/**
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* struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
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* watchdog timer use.
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* @qtimer: QEMU timer that notifies us on expiration.
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* @expires_ns: Absolute virtual expiration time.
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* @remaining_ns: Remaining time until expiration if timer is paused.
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*/
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typedef struct NPCM7xxBaseTimer {
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QEMUTimer qtimer;
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int64_t expires_ns;
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int64_t remaining_ns;
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} NPCM7xxBaseTimer;
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/**
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* struct NPCM7xxTimer - Individual timer state.
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* @ctrl: The timer module that owns this timer.
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* @irq: GIC interrupt line to fire on expiration (if enabled).
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* @base_timer: The basic timer functionality for this timer.
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* @tcsr: The Timer Control and Status Register.
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* @ticr: The Timer Initial Count Register.
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*/
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typedef struct NPCM7xxTimer {
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NPCM7xxTimerCtrlState *ctrl;
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qemu_irq irq;
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NPCM7xxBaseTimer base_timer;
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uint32_t tcsr;
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uint32_t ticr;
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} NPCM7xxTimer;
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/**
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* struct NPCM7xxWatchdogTimer - The watchdog timer state.
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* @ctrl: The timer module that owns this timer.
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* @irq: GIC interrupt line to fire on expiration (if enabled).
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* @reset_signal: The GPIO used to send a reset signal.
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* @base_timer: The basic timer functionality for this timer.
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* @wtcr: The Watchdog Timer Control Register.
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*/
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typedef struct NPCM7xxWatchdogTimer {
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NPCM7xxTimerCtrlState *ctrl;
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qemu_irq irq;
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qemu_irq reset_signal;
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NPCM7xxBaseTimer base_timer;
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uint32_t wtcr;
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} NPCM7xxWatchdogTimer;
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/**
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* struct NPCM7xxTimerCtrlState - Timer Module device state.
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* @parent: System bus device.
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* @iomem: Memory region through which registers are accessed.
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* @index: The index of this timer module.
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* @tisr: The Timer Interrupt Status Register.
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* @timer: The five individual timers managed by this module.
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* @watchdog_timer: The watchdog timer managed by this module.
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*/
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struct NPCM7xxTimerCtrlState {
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SysBusDevice parent;
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MemoryRegion iomem;
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uint32_t tisr;
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Clock *clock;
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NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
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NPCM7xxWatchdogTimer watchdog_timer;
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};
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#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
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#define NPCM7XX_TIMER(obj) \
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OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
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#endif /* NPCM7XX_TIMER_H */
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