mirror of https://gitee.com/openkylin/qemu.git
645 lines
12 KiB
C
645 lines
12 KiB
C
DEF(end, 0)
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DEF(movl_A0_EAX, 0)
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DEF(addl_A0_EAX, 0)
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DEF(addl_A0_EAX_s1, 0)
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DEF(addl_A0_EAX_s2, 0)
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DEF(addl_A0_EAX_s3, 0)
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DEF(movl_T0_EAX, 0)
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DEF(movl_T1_EAX, 0)
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DEF(movh_T0_EAX, 0)
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DEF(movh_T1_EAX, 0)
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DEF(movl_EAX_T0, 0)
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DEF(movl_EAX_T1, 0)
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DEF(movl_EAX_A0, 0)
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DEF(cmovw_EAX_T1_T0, 0)
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DEF(cmovl_EAX_T1_T0, 0)
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DEF(movw_EAX_T0, 0)
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DEF(movw_EAX_T1, 0)
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DEF(movw_EAX_A0, 0)
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DEF(movb_EAX_T0, 0)
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DEF(movh_EAX_T0, 0)
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DEF(movb_EAX_T1, 0)
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DEF(movh_EAX_T1, 0)
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DEF(movl_A0_ECX, 0)
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DEF(addl_A0_ECX, 0)
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DEF(addl_A0_ECX_s1, 0)
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DEF(addl_A0_ECX_s2, 0)
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DEF(addl_A0_ECX_s3, 0)
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DEF(movl_T0_ECX, 0)
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DEF(movl_T1_ECX, 0)
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DEF(movh_T0_ECX, 0)
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DEF(movh_T1_ECX, 0)
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DEF(movl_ECX_T0, 0)
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DEF(movl_ECX_T1, 0)
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DEF(movl_ECX_A0, 0)
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DEF(cmovw_ECX_T1_T0, 0)
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DEF(cmovl_ECX_T1_T0, 0)
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DEF(movw_ECX_T0, 0)
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DEF(movw_ECX_T1, 0)
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DEF(movw_ECX_A0, 0)
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DEF(movb_ECX_T0, 0)
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DEF(movh_ECX_T0, 0)
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DEF(movb_ECX_T1, 0)
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DEF(movh_ECX_T1, 0)
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DEF(movl_A0_EDX, 0)
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DEF(addl_A0_EDX, 0)
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DEF(addl_A0_EDX_s1, 0)
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DEF(addl_A0_EDX_s2, 0)
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DEF(addl_A0_EDX_s3, 0)
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DEF(movl_T0_EDX, 0)
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DEF(movl_T1_EDX, 0)
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DEF(movh_T0_EDX, 0)
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DEF(movh_T1_EDX, 0)
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DEF(movl_EDX_T0, 0)
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DEF(movl_EDX_T1, 0)
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DEF(movl_EDX_A0, 0)
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DEF(cmovw_EDX_T1_T0, 0)
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DEF(cmovl_EDX_T1_T0, 0)
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DEF(movw_EDX_T0, 0)
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DEF(movw_EDX_T1, 0)
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DEF(movw_EDX_A0, 0)
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DEF(movb_EDX_T0, 0)
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DEF(movh_EDX_T0, 0)
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DEF(movb_EDX_T1, 0)
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DEF(movh_EDX_T1, 0)
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DEF(movl_A0_EBX, 0)
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DEF(addl_A0_EBX, 0)
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DEF(addl_A0_EBX_s1, 0)
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DEF(addl_A0_EBX_s2, 0)
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DEF(addl_A0_EBX_s3, 0)
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DEF(movl_T0_EBX, 0)
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DEF(movl_T1_EBX, 0)
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DEF(movh_T0_EBX, 0)
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DEF(movh_T1_EBX, 0)
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DEF(movl_EBX_T0, 0)
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DEF(movl_EBX_T1, 0)
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DEF(movl_EBX_A0, 0)
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DEF(cmovw_EBX_T1_T0, 0)
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DEF(cmovl_EBX_T1_T0, 0)
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DEF(movw_EBX_T0, 0)
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DEF(movw_EBX_T1, 0)
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DEF(movw_EBX_A0, 0)
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DEF(movb_EBX_T0, 0)
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DEF(movh_EBX_T0, 0)
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DEF(movb_EBX_T1, 0)
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DEF(movh_EBX_T1, 0)
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DEF(movl_A0_ESP, 0)
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DEF(addl_A0_ESP, 0)
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DEF(addl_A0_ESP_s1, 0)
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DEF(addl_A0_ESP_s2, 0)
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DEF(addl_A0_ESP_s3, 0)
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DEF(movl_T0_ESP, 0)
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DEF(movl_T1_ESP, 0)
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DEF(movh_T0_ESP, 0)
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DEF(movh_T1_ESP, 0)
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DEF(movl_ESP_T0, 0)
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DEF(movl_ESP_T1, 0)
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DEF(movl_ESP_A0, 0)
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DEF(cmovw_ESP_T1_T0, 0)
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DEF(cmovl_ESP_T1_T0, 0)
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DEF(movw_ESP_T0, 0)
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DEF(movw_ESP_T1, 0)
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DEF(movw_ESP_A0, 0)
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DEF(movb_ESP_T0, 0)
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DEF(movh_ESP_T0, 0)
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DEF(movb_ESP_T1, 0)
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DEF(movh_ESP_T1, 0)
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DEF(movl_A0_EBP, 0)
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DEF(addl_A0_EBP, 0)
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DEF(addl_A0_EBP_s1, 0)
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DEF(addl_A0_EBP_s2, 0)
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DEF(addl_A0_EBP_s3, 0)
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DEF(movl_T0_EBP, 0)
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DEF(movl_T1_EBP, 0)
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DEF(movh_T0_EBP, 0)
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DEF(movh_T1_EBP, 0)
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DEF(movl_EBP_T0, 0)
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DEF(movl_EBP_T1, 0)
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DEF(movl_EBP_A0, 0)
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DEF(cmovw_EBP_T1_T0, 0)
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DEF(cmovl_EBP_T1_T0, 0)
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DEF(movw_EBP_T0, 0)
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DEF(movw_EBP_T1, 0)
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DEF(movw_EBP_A0, 0)
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DEF(movb_EBP_T0, 0)
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DEF(movh_EBP_T0, 0)
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DEF(movb_EBP_T1, 0)
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DEF(movh_EBP_T1, 0)
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DEF(movl_A0_ESI, 0)
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DEF(addl_A0_ESI, 0)
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DEF(addl_A0_ESI_s1, 0)
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DEF(addl_A0_ESI_s2, 0)
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DEF(addl_A0_ESI_s3, 0)
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DEF(movl_T0_ESI, 0)
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DEF(movl_T1_ESI, 0)
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DEF(movh_T0_ESI, 0)
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DEF(movh_T1_ESI, 0)
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DEF(movl_ESI_T0, 0)
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DEF(movl_ESI_T1, 0)
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DEF(movl_ESI_A0, 0)
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DEF(cmovw_ESI_T1_T0, 0)
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DEF(cmovl_ESI_T1_T0, 0)
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DEF(movw_ESI_T0, 0)
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DEF(movw_ESI_T1, 0)
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DEF(movw_ESI_A0, 0)
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DEF(movb_ESI_T0, 0)
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DEF(movh_ESI_T0, 0)
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DEF(movb_ESI_T1, 0)
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DEF(movh_ESI_T1, 0)
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DEF(movl_A0_EDI, 0)
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DEF(addl_A0_EDI, 0)
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DEF(addl_A0_EDI_s1, 0)
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DEF(addl_A0_EDI_s2, 0)
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DEF(addl_A0_EDI_s3, 0)
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DEF(movl_T0_EDI, 0)
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DEF(movl_T1_EDI, 0)
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DEF(movh_T0_EDI, 0)
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DEF(movh_T1_EDI, 0)
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DEF(movl_EDI_T0, 0)
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DEF(movl_EDI_T1, 0)
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DEF(movl_EDI_A0, 0)
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DEF(cmovw_EDI_T1_T0, 0)
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DEF(cmovl_EDI_T1_T0, 0)
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DEF(movw_EDI_T0, 0)
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DEF(movw_EDI_T1, 0)
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DEF(movw_EDI_A0, 0)
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DEF(movb_EDI_T0, 0)
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DEF(movh_EDI_T0, 0)
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DEF(movb_EDI_T1, 0)
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DEF(movh_EDI_T1, 0)
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DEF(addl_T0_T1_cc, 0)
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DEF(orl_T0_T1_cc, 0)
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DEF(andl_T0_T1_cc, 0)
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DEF(subl_T0_T1_cc, 0)
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DEF(xorl_T0_T1_cc, 0)
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DEF(cmpl_T0_T1_cc, 0)
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DEF(negl_T0_cc, 0)
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DEF(incl_T0_cc, 0)
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DEF(decl_T0_cc, 0)
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DEF(testl_T0_T1_cc, 0)
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DEF(addl_T0_T1, 0)
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DEF(orl_T0_T1, 0)
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DEF(andl_T0_T1, 0)
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DEF(subl_T0_T1, 0)
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DEF(xorl_T0_T1, 0)
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DEF(negl_T0, 0)
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DEF(incl_T0, 0)
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DEF(decl_T0, 0)
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DEF(notl_T0, 0)
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DEF(bswapl_T0, 0)
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DEF(mulb_AL_T0, 0)
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DEF(imulb_AL_T0, 0)
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DEF(mulw_AX_T0, 0)
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DEF(imulw_AX_T0, 0)
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DEF(mull_EAX_T0, 0)
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DEF(imull_EAX_T0, 0)
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DEF(imulw_T0_T1, 0)
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DEF(imull_T0_T1, 0)
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DEF(divb_AL_T0, 0)
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DEF(idivb_AL_T0, 0)
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DEF(divw_AX_T0, 0)
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DEF(idivw_AX_T0, 0)
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DEF(divl_EAX_T0, 0)
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DEF(idivl_EAX_T0, 0)
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DEF(movl_T0_im, 1)
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DEF(addl_T0_im, 1)
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DEF(andl_T0_ffff, 0)
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DEF(movl_T0_T1, 0)
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DEF(movl_T1_im, 1)
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DEF(addl_T1_im, 1)
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DEF(movl_T1_A0, 0)
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DEF(movl_A0_im, 1)
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DEF(addl_A0_im, 1)
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DEF(addl_A0_AL, 0)
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DEF(andl_A0_ffff, 0)
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DEF(ldub_T0_A0, 0)
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DEF(ldsb_T0_A0, 0)
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DEF(lduw_T0_A0, 0)
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DEF(ldsw_T0_A0, 0)
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DEF(ldl_T0_A0, 0)
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DEF(ldub_T1_A0, 0)
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DEF(ldsb_T1_A0, 0)
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DEF(lduw_T1_A0, 0)
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DEF(ldsw_T1_A0, 0)
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DEF(ldl_T1_A0, 0)
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DEF(stb_T0_A0, 0)
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DEF(stw_T0_A0, 0)
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DEF(stl_T0_A0, 0)
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DEF(add_bitw_A0_T1, 0)
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DEF(add_bitl_A0_T1, 0)
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DEF(jmp_T0, 0)
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DEF(jmp_im, 1)
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DEF(int_im, 1)
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DEF(int3, 1)
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DEF(into, 0)
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DEF(cli, 0)
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DEF(sti, 0)
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DEF(cli_vm, 0)
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DEF(sti_vm, 1)
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DEF(boundw, 0)
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DEF(boundl, 0)
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DEF(cmpxchg8b, 0)
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DEF(jb_subb, 2)
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DEF(jz_subb, 2)
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DEF(jbe_subb, 2)
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DEF(js_subb, 2)
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DEF(jl_subb, 2)
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DEF(jle_subb, 2)
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DEF(setb_T0_subb, 0)
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DEF(setz_T0_subb, 0)
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DEF(setbe_T0_subb, 0)
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DEF(sets_T0_subb, 0)
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DEF(setl_T0_subb, 0)
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DEF(setle_T0_subb, 0)
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DEF(rolb_T0_T1_cc, 0)
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DEF(rolb_T0_T1, 0)
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DEF(rorb_T0_T1_cc, 0)
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DEF(rorb_T0_T1, 0)
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DEF(rclb_T0_T1_cc, 0)
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DEF(rcrb_T0_T1_cc, 0)
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DEF(shlb_T0_T1_cc, 0)
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DEF(shlb_T0_T1, 0)
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DEF(shrb_T0_T1_cc, 0)
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DEF(shrb_T0_T1, 0)
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DEF(sarb_T0_T1_cc, 0)
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DEF(sarb_T0_T1, 0)
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DEF(adcb_T0_T1_cc, 0)
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DEF(sbbb_T0_T1_cc, 0)
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DEF(cmpxchgb_T0_T1_EAX_cc, 0)
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DEF(movsb_fast, 0)
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DEF(rep_movsb_fast, 0)
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DEF(stosb_fast, 0)
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DEF(rep_stosb_fast, 0)
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DEF(lodsb_fast, 0)
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DEF(rep_lodsb_fast, 0)
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DEF(scasb_fast, 0)
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DEF(repz_scasb_fast, 0)
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DEF(repnz_scasb_fast, 0)
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DEF(cmpsb_fast, 0)
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DEF(repz_cmpsb_fast, 0)
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DEF(repnz_cmpsb_fast, 0)
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DEF(outsb_fast, 0)
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DEF(rep_outsb_fast, 0)
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DEF(insb_fast, 0)
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DEF(rep_insb_fast, 0)
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DEF(movsb_a32, 0)
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DEF(rep_movsb_a32, 0)
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DEF(stosb_a32, 0)
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DEF(rep_stosb_a32, 0)
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DEF(lodsb_a32, 0)
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DEF(rep_lodsb_a32, 0)
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DEF(scasb_a32, 0)
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DEF(repz_scasb_a32, 0)
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DEF(repnz_scasb_a32, 0)
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DEF(cmpsb_a32, 0)
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DEF(repz_cmpsb_a32, 0)
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DEF(repnz_cmpsb_a32, 0)
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DEF(outsb_a32, 0)
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DEF(rep_outsb_a32, 0)
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DEF(insb_a32, 0)
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DEF(rep_insb_a32, 0)
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DEF(movsb_a16, 0)
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DEF(rep_movsb_a16, 0)
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DEF(stosb_a16, 0)
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DEF(rep_stosb_a16, 0)
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DEF(lodsb_a16, 0)
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DEF(rep_lodsb_a16, 0)
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DEF(scasb_a16, 0)
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DEF(repz_scasb_a16, 0)
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DEF(repnz_scasb_a16, 0)
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DEF(cmpsb_a16, 0)
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DEF(repz_cmpsb_a16, 0)
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DEF(repnz_cmpsb_a16, 0)
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DEF(outsb_a16, 0)
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DEF(rep_outsb_a16, 0)
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DEF(insb_a16, 0)
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DEF(rep_insb_a16, 0)
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DEF(outb_T0_T1, 0)
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DEF(inb_T0_T1, 0)
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DEF(jb_subw, 2)
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DEF(jz_subw, 2)
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DEF(jbe_subw, 2)
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DEF(js_subw, 2)
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DEF(jl_subw, 2)
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DEF(jle_subw, 2)
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DEF(loopnzw, 2)
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DEF(loopzw, 2)
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DEF(loopw, 2)
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DEF(jecxzw, 2)
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DEF(setb_T0_subw, 0)
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DEF(setz_T0_subw, 0)
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DEF(setbe_T0_subw, 0)
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DEF(sets_T0_subw, 0)
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DEF(setl_T0_subw, 0)
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DEF(setle_T0_subw, 0)
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DEF(rolw_T0_T1_cc, 0)
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DEF(rolw_T0_T1, 0)
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DEF(rorw_T0_T1_cc, 0)
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DEF(rorw_T0_T1, 0)
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DEF(rclw_T0_T1_cc, 0)
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DEF(rcrw_T0_T1_cc, 0)
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DEF(shlw_T0_T1_cc, 0)
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DEF(shlw_T0_T1, 0)
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DEF(shrw_T0_T1_cc, 0)
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DEF(shrw_T0_T1, 0)
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DEF(sarw_T0_T1_cc, 0)
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DEF(sarw_T0_T1, 0)
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DEF(shldw_T0_T1_im_cc, 1)
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DEF(shldw_T0_T1_ECX_cc, 0)
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DEF(shrdw_T0_T1_im_cc, 1)
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DEF(shrdw_T0_T1_ECX_cc, 0)
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DEF(adcw_T0_T1_cc, 0)
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DEF(sbbw_T0_T1_cc, 0)
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DEF(cmpxchgw_T0_T1_EAX_cc, 0)
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DEF(btw_T0_T1_cc, 0)
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DEF(btsw_T0_T1_cc, 0)
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DEF(btrw_T0_T1_cc, 0)
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DEF(btcw_T0_T1_cc, 0)
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DEF(bsfw_T0_cc, 0)
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DEF(bsrw_T0_cc, 0)
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DEF(movsw_fast, 0)
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DEF(rep_movsw_fast, 0)
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DEF(stosw_fast, 0)
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DEF(rep_stosw_fast, 0)
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DEF(lodsw_fast, 0)
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DEF(rep_lodsw_fast, 0)
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DEF(scasw_fast, 0)
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DEF(repz_scasw_fast, 0)
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DEF(repnz_scasw_fast, 0)
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DEF(cmpsw_fast, 0)
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DEF(repz_cmpsw_fast, 0)
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DEF(repnz_cmpsw_fast, 0)
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DEF(outsw_fast, 0)
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DEF(rep_outsw_fast, 0)
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DEF(insw_fast, 0)
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DEF(rep_insw_fast, 0)
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DEF(movsw_a32, 0)
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DEF(rep_movsw_a32, 0)
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DEF(stosw_a32, 0)
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DEF(rep_stosw_a32, 0)
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DEF(lodsw_a32, 0)
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DEF(rep_lodsw_a32, 0)
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DEF(scasw_a32, 0)
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DEF(repz_scasw_a32, 0)
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DEF(repnz_scasw_a32, 0)
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DEF(cmpsw_a32, 0)
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DEF(repz_cmpsw_a32, 0)
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DEF(repnz_cmpsw_a32, 0)
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DEF(outsw_a32, 0)
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DEF(rep_outsw_a32, 0)
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DEF(insw_a32, 0)
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DEF(rep_insw_a32, 0)
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|
DEF(movsw_a16, 0)
|
|
DEF(rep_movsw_a16, 0)
|
|
DEF(stosw_a16, 0)
|
|
DEF(rep_stosw_a16, 0)
|
|
DEF(lodsw_a16, 0)
|
|
DEF(rep_lodsw_a16, 0)
|
|
DEF(scasw_a16, 0)
|
|
DEF(repz_scasw_a16, 0)
|
|
DEF(repnz_scasw_a16, 0)
|
|
DEF(cmpsw_a16, 0)
|
|
DEF(repz_cmpsw_a16, 0)
|
|
DEF(repnz_cmpsw_a16, 0)
|
|
DEF(outsw_a16, 0)
|
|
DEF(rep_outsw_a16, 0)
|
|
DEF(insw_a16, 0)
|
|
DEF(rep_insw_a16, 0)
|
|
DEF(outw_T0_T1, 0)
|
|
DEF(inw_T0_T1, 0)
|
|
DEF(jb_subl, 2)
|
|
DEF(jz_subl, 2)
|
|
DEF(jbe_subl, 2)
|
|
DEF(js_subl, 2)
|
|
DEF(jl_subl, 2)
|
|
DEF(jle_subl, 2)
|
|
DEF(loopnzl, 2)
|
|
DEF(loopzl, 2)
|
|
DEF(loopl, 2)
|
|
DEF(jecxzl, 2)
|
|
DEF(setb_T0_subl, 0)
|
|
DEF(setz_T0_subl, 0)
|
|
DEF(setbe_T0_subl, 0)
|
|
DEF(sets_T0_subl, 0)
|
|
DEF(setl_T0_subl, 0)
|
|
DEF(setle_T0_subl, 0)
|
|
DEF(roll_T0_T1_cc, 0)
|
|
DEF(roll_T0_T1, 0)
|
|
DEF(rorl_T0_T1_cc, 0)
|
|
DEF(rorl_T0_T1, 0)
|
|
DEF(rcll_T0_T1_cc, 0)
|
|
DEF(rcrl_T0_T1_cc, 0)
|
|
DEF(shll_T0_T1_cc, 0)
|
|
DEF(shll_T0_T1, 0)
|
|
DEF(shrl_T0_T1_cc, 0)
|
|
DEF(shrl_T0_T1, 0)
|
|
DEF(sarl_T0_T1_cc, 0)
|
|
DEF(sarl_T0_T1, 0)
|
|
DEF(shldl_T0_T1_im_cc, 1)
|
|
DEF(shldl_T0_T1_ECX_cc, 0)
|
|
DEF(shrdl_T0_T1_im_cc, 1)
|
|
DEF(shrdl_T0_T1_ECX_cc, 0)
|
|
DEF(adcl_T0_T1_cc, 0)
|
|
DEF(sbbl_T0_T1_cc, 0)
|
|
DEF(cmpxchgl_T0_T1_EAX_cc, 0)
|
|
DEF(btl_T0_T1_cc, 0)
|
|
DEF(btsl_T0_T1_cc, 0)
|
|
DEF(btrl_T0_T1_cc, 0)
|
|
DEF(btcl_T0_T1_cc, 0)
|
|
DEF(bsfl_T0_cc, 0)
|
|
DEF(bsrl_T0_cc, 0)
|
|
DEF(movsl_fast, 0)
|
|
DEF(rep_movsl_fast, 0)
|
|
DEF(stosl_fast, 0)
|
|
DEF(rep_stosl_fast, 0)
|
|
DEF(lodsl_fast, 0)
|
|
DEF(rep_lodsl_fast, 0)
|
|
DEF(scasl_fast, 0)
|
|
DEF(repz_scasl_fast, 0)
|
|
DEF(repnz_scasl_fast, 0)
|
|
DEF(cmpsl_fast, 0)
|
|
DEF(repz_cmpsl_fast, 0)
|
|
DEF(repnz_cmpsl_fast, 0)
|
|
DEF(outsl_fast, 0)
|
|
DEF(rep_outsl_fast, 0)
|
|
DEF(insl_fast, 0)
|
|
DEF(rep_insl_fast, 0)
|
|
DEF(movsl_a32, 0)
|
|
DEF(rep_movsl_a32, 0)
|
|
DEF(stosl_a32, 0)
|
|
DEF(rep_stosl_a32, 0)
|
|
DEF(lodsl_a32, 0)
|
|
DEF(rep_lodsl_a32, 0)
|
|
DEF(scasl_a32, 0)
|
|
DEF(repz_scasl_a32, 0)
|
|
DEF(repnz_scasl_a32, 0)
|
|
DEF(cmpsl_a32, 0)
|
|
DEF(repz_cmpsl_a32, 0)
|
|
DEF(repnz_cmpsl_a32, 0)
|
|
DEF(outsl_a32, 0)
|
|
DEF(rep_outsl_a32, 0)
|
|
DEF(insl_a32, 0)
|
|
DEF(rep_insl_a32, 0)
|
|
DEF(movsl_a16, 0)
|
|
DEF(rep_movsl_a16, 0)
|
|
DEF(stosl_a16, 0)
|
|
DEF(rep_stosl_a16, 0)
|
|
DEF(lodsl_a16, 0)
|
|
DEF(rep_lodsl_a16, 0)
|
|
DEF(scasl_a16, 0)
|
|
DEF(repz_scasl_a16, 0)
|
|
DEF(repnz_scasl_a16, 0)
|
|
DEF(cmpsl_a16, 0)
|
|
DEF(repz_cmpsl_a16, 0)
|
|
DEF(repnz_cmpsl_a16, 0)
|
|
DEF(outsl_a16, 0)
|
|
DEF(rep_outsl_a16, 0)
|
|
DEF(insl_a16, 0)
|
|
DEF(rep_insl_a16, 0)
|
|
DEF(outl_T0_T1, 0)
|
|
DEF(inl_T0_T1, 0)
|
|
DEF(movsbl_T0_T0, 0)
|
|
DEF(movzbl_T0_T0, 0)
|
|
DEF(movswl_T0_T0, 0)
|
|
DEF(movzwl_T0_T0, 0)
|
|
DEF(movswl_EAX_AX, 0)
|
|
DEF(movsbw_AX_AL, 0)
|
|
DEF(movslq_EDX_EAX, 0)
|
|
DEF(movswl_DX_AX, 0)
|
|
DEF(pushl_T0, 0)
|
|
DEF(pushw_T0, 0)
|
|
DEF(pushl_ss32_T0, 0)
|
|
DEF(pushw_ss32_T0, 0)
|
|
DEF(pushl_ss16_T0, 0)
|
|
DEF(pushw_ss16_T0, 0)
|
|
DEF(popl_T0, 0)
|
|
DEF(popw_T0, 0)
|
|
DEF(popl_ss32_T0, 0)
|
|
DEF(popw_ss32_T0, 0)
|
|
DEF(popl_ss16_T0, 0)
|
|
DEF(popw_ss16_T0, 0)
|
|
DEF(addl_ESP_4, 0)
|
|
DEF(addl_ESP_2, 0)
|
|
DEF(addw_ESP_4, 0)
|
|
DEF(addw_ESP_2, 0)
|
|
DEF(addl_ESP_im, 1)
|
|
DEF(addw_ESP_im, 1)
|
|
DEF(rdtsc, 0)
|
|
DEF(cpuid, 0)
|
|
DEF(aam, 1)
|
|
DEF(aad, 1)
|
|
DEF(aaa, 0)
|
|
DEF(aas, 0)
|
|
DEF(daa, 0)
|
|
DEF(das, 0)
|
|
DEF(movl_seg_T0, 1)
|
|
DEF(movl_T0_seg, 1)
|
|
DEF(movl_A0_seg, 1)
|
|
DEF(addl_A0_seg, 1)
|
|
DEF(jo_cc, 2)
|
|
DEF(jb_cc, 2)
|
|
DEF(jz_cc, 2)
|
|
DEF(jbe_cc, 2)
|
|
DEF(js_cc, 2)
|
|
DEF(jp_cc, 2)
|
|
DEF(jl_cc, 2)
|
|
DEF(jle_cc, 2)
|
|
DEF(seto_T0_cc, 0)
|
|
DEF(setb_T0_cc, 0)
|
|
DEF(setz_T0_cc, 0)
|
|
DEF(setbe_T0_cc, 0)
|
|
DEF(sets_T0_cc, 0)
|
|
DEF(setp_T0_cc, 0)
|
|
DEF(setl_T0_cc, 0)
|
|
DEF(setle_T0_cc, 0)
|
|
DEF(xor_T0_1, 0)
|
|
DEF(set_cc_op, 1)
|
|
DEF(movl_eflags_T0, 0)
|
|
DEF(movw_eflags_T0, 0)
|
|
DEF(movw_eflags_T0_vm, 1)
|
|
DEF(movl_eflags_T0_vm, 1)
|
|
DEF(movb_eflags_T0, 0)
|
|
DEF(movl_T0_eflags, 0)
|
|
DEF(movl_T0_eflags_vm, 0)
|
|
DEF(cld, 0)
|
|
DEF(std, 0)
|
|
DEF(clc, 0)
|
|
DEF(stc, 0)
|
|
DEF(cmc, 0)
|
|
DEF(salc, 0)
|
|
DEF(flds_FT0_A0, 0)
|
|
DEF(fldl_FT0_A0, 0)
|
|
DEF(fild_FT0_A0, 0)
|
|
DEF(fildl_FT0_A0, 0)
|
|
DEF(fildll_FT0_A0, 0)
|
|
DEF(flds_ST0_A0, 0)
|
|
DEF(fldl_ST0_A0, 0)
|
|
DEF(fldt_ST0_A0, 0)
|
|
DEF(fild_ST0_A0, 0)
|
|
DEF(fildl_ST0_A0, 0)
|
|
DEF(fildll_ST0_A0, 0)
|
|
DEF(fsts_ST0_A0, 0)
|
|
DEF(fstl_ST0_A0, 0)
|
|
DEF(fstt_ST0_A0, 0)
|
|
DEF(fist_ST0_A0, 0)
|
|
DEF(fistl_ST0_A0, 0)
|
|
DEF(fistll_ST0_A0, 0)
|
|
DEF(fbld_ST0_A0, 0)
|
|
DEF(fbst_ST0_A0, 0)
|
|
DEF(fpush, 0)
|
|
DEF(fpop, 0)
|
|
DEF(fdecstp, 0)
|
|
DEF(fincstp, 0)
|
|
DEF(fmov_ST0_FT0, 0)
|
|
DEF(fmov_FT0_STN, 1)
|
|
DEF(fmov_ST0_STN, 1)
|
|
DEF(fmov_STN_ST0, 1)
|
|
DEF(fxchg_ST0_STN, 1)
|
|
DEF(fcom_ST0_FT0, 0)
|
|
DEF(fucom_ST0_FT0, 0)
|
|
DEF(fadd_ST0_FT0, 0)
|
|
DEF(fmul_ST0_FT0, 0)
|
|
DEF(fsub_ST0_FT0, 0)
|
|
DEF(fsubr_ST0_FT0, 0)
|
|
DEF(fdiv_ST0_FT0, 0)
|
|
DEF(fdivr_ST0_FT0, 0)
|
|
DEF(fadd_STN_ST0, 1)
|
|
DEF(fmul_STN_ST0, 1)
|
|
DEF(fsub_STN_ST0, 1)
|
|
DEF(fsubr_STN_ST0, 1)
|
|
DEF(fdiv_STN_ST0, 1)
|
|
DEF(fdivr_STN_ST0, 1)
|
|
DEF(fchs_ST0, 0)
|
|
DEF(fabs_ST0, 0)
|
|
DEF(fxam_ST0, 0)
|
|
DEF(fld1_ST0, 0)
|
|
DEF(fldl2t_ST0, 0)
|
|
DEF(fldl2e_ST0, 0)
|
|
DEF(fldpi_ST0, 0)
|
|
DEF(fldlg2_ST0, 0)
|
|
DEF(fldln2_ST0, 0)
|
|
DEF(fldz_ST0, 0)
|
|
DEF(fldz_FT0, 0)
|
|
DEF(f2xm1, 0)
|
|
DEF(fyl2x, 0)
|
|
DEF(fptan, 0)
|
|
DEF(fpatan, 0)
|
|
DEF(fxtract, 0)
|
|
DEF(fprem1, 0)
|
|
DEF(fprem, 0)
|
|
DEF(fyl2xp1, 0)
|
|
DEF(fsqrt, 0)
|
|
DEF(fsincos, 0)
|
|
DEF(frndint, 0)
|
|
DEF(fscale, 0)
|
|
DEF(fsin, 0)
|
|
DEF(fcos, 0)
|
|
DEF(fnstsw_A0, 0)
|
|
DEF(fnstsw_EAX, 0)
|
|
DEF(fnstcw_A0, 0)
|
|
DEF(fldcw_A0, 0)
|
|
DEF(fclex, 0)
|
|
DEF(fninit, 0)
|
|
DEF(lock, 0)
|
|
DEF(unlock, 0)
|