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qemu/target-tricore
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Bastian Koppelmann 2b2f7d97d8 target-tricore: Add instructions of RLC opcode format 
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
 		2014-12-10 11:13:45 +00:00
..
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Make TRICORE_FEATURES implying others. 2014-12-10 11:13:45 +00:00
cpu.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
csfr.def target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
op_helper.c target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
translate.c target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00