mirror of https://gitee.com/openkylin/qemu.git
648 lines
16 KiB
C
648 lines
16 KiB
C
/*
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* PowerPC gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "exec/helper-proto.h"
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#include "internal.h"
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static int ppc_gdb_register_len_apple(int n)
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{
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switch (n) {
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case 0 ... 31:
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/* gprs */
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return 8;
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case 32 ... 63:
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/* fprs */
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return 8;
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case 64 ... 95:
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return 16;
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case 64 + 32: /* nip */
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case 65 + 32: /* msr */
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case 67 + 32: /* lr */
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case 68 + 32: /* ctr */
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case 70 + 32: /* fpscr */
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return 8;
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case 66 + 32: /* cr */
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case 69 + 32: /* xer */
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return 4;
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default:
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return 0;
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}
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}
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static int ppc_gdb_register_len(int n)
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{
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switch (n) {
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case 0 ... 31:
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/* gprs */
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return sizeof(target_ulong);
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case 32 ... 63:
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/* fprs */
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if (gdb_has_xml) {
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return 0;
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}
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return 8;
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case 66:
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/* cr */
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case 69:
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/* xer */
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return 4;
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case 64:
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/* nip */
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case 65:
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/* msr */
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case 67:
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/* lr */
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case 68:
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/* ctr */
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return sizeof(target_ulong);
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case 70:
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/* fpscr */
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if (gdb_has_xml) {
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return 0;
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}
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return sizeof(target_ulong);
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default:
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return 0;
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}
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}
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/*
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* We need to present the registers to gdb in the "current" memory
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* ordering. For user-only mode we get this for free;
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* TARGET_WORDS_BIGENDIAN is set to the proper ordering for the
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* binary, and cannot be changed. For system mode,
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* TARGET_WORDS_BIGENDIAN is always set, and we must check the current
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* mode of the chip to see if we're running in little-endian.
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*/
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void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
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{
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#ifndef CONFIG_USER_ONLY
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if (!msr_le) {
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/* do nothing */
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} else if (len == 4) {
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bswap32s((uint32_t *)mem_buf);
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} else if (len == 8) {
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bswap64s((uint64_t *)mem_buf);
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} else {
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g_assert_not_reached();
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}
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#endif
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}
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/*
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* Old gdb always expects FP registers. Newer (xml-aware) gdb only
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* expects whatever the target description contains. Due to a
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* historical mishap the FP registers appear in between core integer
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* regs and PC, MSR, CR, and so forth. We hack round this by giving
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* the FP regs zero size when talking to a newer gdb.
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*/
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int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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uint8_t *mem_buf;
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int r = ppc_gdb_register_len(n);
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if (!r) {
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return r;
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}
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if (n < 32) {
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/* gprs */
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gdb_get_regl(buf, env->gpr[n]);
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} else if (n < 64) {
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/* fprs */
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gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
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} else {
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switch (n) {
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case 64:
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gdb_get_regl(buf, env->nip);
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break;
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case 65:
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gdb_get_regl(buf, env->msr);
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break;
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case 66:
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{
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uint32_t cr = 0;
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int i;
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for (i = 0; i < 8; i++) {
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cr |= env->crf[i] << (32 - ((i + 1) * 4));
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}
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gdb_get_reg32(buf, cr);
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break;
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}
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case 67:
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gdb_get_regl(buf, env->lr);
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break;
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case 68:
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gdb_get_regl(buf, env->ctr);
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break;
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case 69:
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gdb_get_reg32(buf, env->xer);
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break;
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case 70:
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gdb_get_reg32(buf, env->fpscr);
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break;
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}
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}
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mem_buf = buf->data + buf->len - r;
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ppc_maybe_bswap_register(env, mem_buf, r);
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return r;
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}
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int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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uint8_t *mem_buf;
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int r = ppc_gdb_register_len_apple(n);
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if (!r) {
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return r;
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}
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if (n < 32) {
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/* gprs */
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gdb_get_reg64(buf, env->gpr[n]);
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} else if (n < 64) {
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/* fprs */
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gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
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} else if (n < 96) {
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/* Altivec */
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gdb_get_reg64(buf, n - 64);
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gdb_get_reg64(buf, 0);
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} else {
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switch (n) {
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case 64 + 32:
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gdb_get_reg64(buf, env->nip);
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break;
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case 65 + 32:
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gdb_get_reg64(buf, env->msr);
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break;
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case 66 + 32:
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{
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uint32_t cr = 0;
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int i;
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for (i = 0; i < 8; i++) {
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cr |= env->crf[i] << (32 - ((i + 1) * 4));
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}
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gdb_get_reg32(buf, cr);
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break;
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}
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case 67 + 32:
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gdb_get_reg64(buf, env->lr);
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break;
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case 68 + 32:
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gdb_get_reg64(buf, env->ctr);
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break;
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case 69 + 32:
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gdb_get_reg32(buf, env->xer);
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break;
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case 70 + 32:
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gdb_get_reg64(buf, env->fpscr);
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break;
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}
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}
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mem_buf = buf->data + buf->len - r;
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ppc_maybe_bswap_register(env, mem_buf, r);
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return r;
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}
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int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len(n);
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if (!r) {
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return r;
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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if (n < 32) {
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/* gprs */
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env->gpr[n] = ldtul_p(mem_buf);
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} else if (n < 64) {
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/* fprs */
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*cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
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} else {
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switch (n) {
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case 64:
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env->nip = ldtul_p(mem_buf);
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break;
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case 65:
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ppc_store_msr(env, ldtul_p(mem_buf));
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break;
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case 66:
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{
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uint32_t cr = ldl_p(mem_buf);
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int i;
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for (i = 0; i < 8; i++) {
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env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
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}
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break;
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}
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case 67:
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env->lr = ldtul_p(mem_buf);
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break;
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case 68:
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env->ctr = ldtul_p(mem_buf);
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break;
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case 69:
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env->xer = ldl_p(mem_buf);
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break;
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case 70:
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/* fpscr */
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store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
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break;
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}
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}
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return r;
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}
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int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int r = ppc_gdb_register_len_apple(n);
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if (!r) {
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return r;
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}
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ppc_maybe_bswap_register(env, mem_buf, r);
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if (n < 32) {
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/* gprs */
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env->gpr[n] = ldq_p(mem_buf);
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} else if (n < 64) {
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/* fprs */
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*cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
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} else {
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switch (n) {
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case 64 + 32:
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env->nip = ldq_p(mem_buf);
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break;
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case 65 + 32:
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ppc_store_msr(env, ldq_p(mem_buf));
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break;
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case 66 + 32:
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{
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uint32_t cr = ldl_p(mem_buf);
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int i;
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for (i = 0; i < 8; i++) {
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env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
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}
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break;
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}
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case 67 + 32:
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env->lr = ldq_p(mem_buf);
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break;
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case 68 + 32:
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env->ctr = ldq_p(mem_buf);
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break;
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case 69 + 32:
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env->xer = ldl_p(mem_buf);
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break;
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case 70 + 32:
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/* fpscr */
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store_fpscr(env, ldq_p(mem_buf), 0xffffffff);
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break;
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}
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}
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return r;
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}
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#ifndef CONFIG_USER_ONLY
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void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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GString *xml;
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char *spr_name;
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unsigned int num_regs = 0;
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int i;
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if (pcc->gdb_spr_xml) {
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return;
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}
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xml = g_string_new("<?xml version=\"1.0\"?>");
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g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
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for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
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ppc_spr_t *spr = &env->spr_cb[i];
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if (!spr->name) {
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continue;
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}
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spr_name = g_ascii_strdown(spr->name, -1);
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g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
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g_free(spr_name);
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g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
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g_string_append(xml, " group=\"spr\"/>");
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/*
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* GDB identifies registers based on the order they are
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* presented in the XML. These ids will not match QEMU's
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* representation (which follows the PowerISA).
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*
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* Store the position of the current register description so
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* we can make the correspondence later.
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*/
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spr->gdb_id = num_regs;
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num_regs++;
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}
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g_string_append(xml, "</feature>");
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pcc->gdb_num_sprs = num_regs;
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pcc->gdb_spr_xml = g_string_free(xml, false);
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}
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const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
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if (strcmp(xml_name, "power-spr.xml") == 0) {
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return pcc->gdb_spr_xml;
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}
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return NULL;
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}
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#endif
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static bool avr_need_swap(CPUPPCState *env)
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{
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#ifdef HOST_WORDS_BIGENDIAN
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return msr_le;
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#else
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return !msr_le;
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#endif
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}
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#if !defined(CONFIG_USER_ONLY)
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static int gdb_find_spr_idx(CPUPPCState *env, int n)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
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ppc_spr_t *spr = &env->spr_cb[i];
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if (spr->name && spr->gdb_id == n) {
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return i;
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}
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}
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return -1;
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}
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static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
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{
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int reg;
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int len;
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reg = gdb_find_spr_idx(env, n);
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if (reg < 0) {
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return 0;
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}
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len = TARGET_LONG_SIZE;
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gdb_get_regl(buf, env->spr[reg]);
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ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
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return len;
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}
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static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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int reg;
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int len;
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reg = gdb_find_spr_idx(env, n);
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if (reg < 0) {
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return 0;
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}
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len = TARGET_LONG_SIZE;
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ppc_maybe_bswap_register(env, mem_buf, len);
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env->spr[reg] = ldn_p(mem_buf, len);
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return len;
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}
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#endif
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static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
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{
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uint8_t *mem_buf;
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if (n < 32) {
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gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
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mem_buf = gdb_get_reg_ptr(buf, 8);
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ppc_maybe_bswap_register(env, mem_buf, 8);
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return 8;
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}
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if (n == 32) {
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gdb_get_reg32(buf, env->fpscr);
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mem_buf = gdb_get_reg_ptr(buf, 4);
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ppc_maybe_bswap_register(env, mem_buf, 4);
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return 4;
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}
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return 0;
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}
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static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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ppc_maybe_bswap_register(env, mem_buf, 8);
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*cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
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return 8;
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}
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if (n == 32) {
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ppc_maybe_bswap_register(env, mem_buf, 4);
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store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
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return 4;
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}
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return 0;
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}
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static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
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{
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uint8_t *mem_buf;
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if (n < 32) {
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ppc_avr_t *avr = cpu_avr_ptr(env, n);
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if (!avr_need_swap(env)) {
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gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
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} else {
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gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
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}
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mem_buf = gdb_get_reg_ptr(buf, 16);
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ppc_maybe_bswap_register(env, mem_buf, 8);
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ppc_maybe_bswap_register(env, mem_buf + 8, 8);
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return 16;
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}
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if (n == 32) {
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gdb_get_reg32(buf, ppc_get_vscr(env));
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mem_buf = gdb_get_reg_ptr(buf, 4);
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ppc_maybe_bswap_register(env, mem_buf, 4);
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return 4;
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}
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if (n == 33) {
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gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
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mem_buf = gdb_get_reg_ptr(buf, 4);
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ppc_maybe_bswap_register(env, mem_buf, 4);
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return 4;
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}
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return 0;
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}
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static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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ppc_avr_t *avr = cpu_avr_ptr(env, n);
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ppc_maybe_bswap_register(env, mem_buf, 8);
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ppc_maybe_bswap_register(env, mem_buf + 8, 8);
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if (!avr_need_swap(env)) {
|
|
avr->u64[0] = ldq_p(mem_buf);
|
|
avr->u64[1] = ldq_p(mem_buf + 8);
|
|
} else {
|
|
avr->u64[1] = ldq_p(mem_buf);
|
|
avr->u64[0] = ldq_p(mem_buf + 8);
|
|
}
|
|
return 16;
|
|
}
|
|
if (n == 32) {
|
|
ppc_maybe_bswap_register(env, mem_buf, 4);
|
|
ppc_store_vscr(env, ldl_p(mem_buf));
|
|
return 4;
|
|
}
|
|
if (n == 33) {
|
|
ppc_maybe_bswap_register(env, mem_buf, 4);
|
|
env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
|
|
return 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
|
|
{
|
|
if (n < 32) {
|
|
#if defined(TARGET_PPC64)
|
|
gdb_get_reg32(buf, env->gpr[n] >> 32);
|
|
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
|
|
#else
|
|
gdb_get_reg32(buf, env->gprh[n]);
|
|
#endif
|
|
return 4;
|
|
}
|
|
if (n == 32) {
|
|
gdb_get_reg64(buf, env->spe_acc);
|
|
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
|
|
return 8;
|
|
}
|
|
if (n == 33) {
|
|
gdb_get_reg32(buf, env->spe_fscr);
|
|
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
|
|
return 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
|
|
{
|
|
if (n < 32) {
|
|
#if defined(TARGET_PPC64)
|
|
target_ulong lo = (uint32_t)env->gpr[n];
|
|
target_ulong hi;
|
|
|
|
ppc_maybe_bswap_register(env, mem_buf, 4);
|
|
|
|
hi = (target_ulong)ldl_p(mem_buf) << 32;
|
|
env->gpr[n] = lo | hi;
|
|
#else
|
|
env->gprh[n] = ldl_p(mem_buf);
|
|
#endif
|
|
return 4;
|
|
}
|
|
if (n == 32) {
|
|
ppc_maybe_bswap_register(env, mem_buf, 8);
|
|
env->spe_acc = ldq_p(mem_buf);
|
|
return 8;
|
|
}
|
|
if (n == 33) {
|
|
ppc_maybe_bswap_register(env, mem_buf, 4);
|
|
env->spe_fscr = ldl_p(mem_buf);
|
|
return 4;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
|
|
{
|
|
if (n < 32) {
|
|
gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
|
|
ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
|
|
return 8;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
|
|
{
|
|
if (n < 32) {
|
|
ppc_maybe_bswap_register(env, mem_buf, 8);
|
|
*cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
|
|
return 8;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
gchar *ppc_gdb_arch_name(CPUState *cs)
|
|
{
|
|
#if defined(TARGET_PPC64)
|
|
return g_strdup("powerpc:common64");
|
|
#else
|
|
return g_strdup("powerpc:common");
|
|
#endif
|
|
}
|
|
|
|
void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
|
|
{
|
|
if (pcc->insns_flags & PPC_FLOAT) {
|
|
gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
|
|
33, "power-fpu.xml", 0);
|
|
}
|
|
if (pcc->insns_flags & PPC_ALTIVEC) {
|
|
gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
|
|
34, "power-altivec.xml", 0);
|
|
}
|
|
if (pcc->insns_flags & PPC_SPE) {
|
|
gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
|
|
34, "power-spe.xml", 0);
|
|
}
|
|
if (pcc->insns_flags2 & PPC2_VSX) {
|
|
gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
|
|
32, "power-vsx.xml", 0);
|
|
}
|
|
#ifndef CONFIG_USER_ONLY
|
|
gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
|
|
pcc->gdb_num_sprs, "power-spr.xml", 0);
|
|
#endif
|
|
}
|