qemu/target-arm
balrog 2e23213f26 Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
2007-08-01 02:31:54 +00:00
..
nwfpe compilation fix 2006-10-29 15:10:09 +00:00
cpu.h Basic OMAP310 support. Basic Palm Tungsten|E machine emulation. 2007-07-29 17:57:26 +00:00
exec.h Clean up of some target specifics in exec.c/cpu-exec.c. 2007-06-03 17:44:37 +00:00
helper.c Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class. 2007-08-01 02:31:54 +00:00
op.c Thumb shifter carry flag fixes. 2007-07-22 18:16:42 +00:00
op_helper.c Add Arm926 core support. 2006-02-20 00:33:36 +00:00
op_iwmmxt.c Implement iwMMXt instruction set for the PXA270 cpu. 2007-04-30 02:02:17 +00:00
op_mem.h Implement iwMMXt instruction set for the PXA270 cpu. 2007-04-30 02:02:17 +00:00
op_template.h armv5te support (Paul Brook) 2005-01-31 20:45:13 +00:00
translate.c Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class. 2007-08-01 02:31:54 +00:00