Aurelien Jarno d42320c26a target-mips: remove MAX_OP_PER_INSTR workaround ... Now that MAX_OP_PER_INSTR has been increased to a safer value, removed the target-mips specific workaround. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2009-09-23 09:25:03 +02:00
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TODO	Move the active FPU registers into env again, and use more TCG registers	2008-09-18 11:57:27 +00:00
cpu.h	cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal	2009-08-24 08:21:42 -05:00
exec.h	qemu: per-arch cpu_has_work (Marcelo Tosatti)	2009-04-24 18:03:20 +00:00
helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
helper.h	target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpers	2009-04-06 12:34:07 +00:00
machine.c	Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64	2009-06-13 15:09:38 +00:00
mips-defs.h	Hardware convenience library	2009-05-19 16:17:58 +01:00
op_helper.c	Add 'static' to please Sparse	2009-09-21 18:39:26 +00:00
translate.c	target-mips: remove MAX_OP_PER_INSTR workaround	2009-09-23 09:25:03 +02:00
translate_init.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00