mirror of https://gitee.com/openkylin/qemu.git
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
|
|
* Spike machine interface
|
|
*
|
|
* Copyright (c) 2017 SiFive, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef HW_RISCV_SPIKE_H
|
|
#define HW_RISCV_SPIKE_H
|
|
|
|
typedef struct {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
RISCVHartArrayState soc;
|
|
void *fdt;
|
|
int fdt_size;
|
|
} SpikeState;
|
|
|
|
enum {
|
|
SPIKE_MROM,
|
|
SPIKE_CLINT,
|
|
SPIKE_DRAM
|
|
};
|
|
|
|
enum {
|
|
SPIKE_CLOCK_FREQ = 1000000000
|
|
};
|
|
|
|
#if defined(TARGET_RISCV32)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
|
|
#elif defined(TARGET_RISCV64)
|
|
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
|
|
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
|
|
#endif
|
|
|
|
#endif
|