aurel32 79d342dc6b tcg/x86_64: optimize register allocation order ... The beginning of the register allocation order list on the TCG x86_64 target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. The same way register %rsi and %rdi are at the top of the register allocation order list, while they can't be used for load/store operations. This means the data and/or address registers are very often %rsi and %rdi, and their values have to be spilled, and then moved back to another register. This patches changes to the allocation order to avoid those effects. It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file, and a 6% gain in qemu-system-mips64 to compile a small application. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162		2009-04-05 20:08:50 +00:00
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tcg-target.c	tcg/x86_64: optimize register allocation order	2009-04-05 20:08:50 +00:00
tcg-target.h	tcg/x86_64: add bswap16_i{32,64} and bswap32_i64 ops	2009-03-13 09:35:55 +00:00