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qemu/target-tricore
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Bastian Koppelmann 9371557115 target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
 		2015-05-22 17:02:34 +02:00
..
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: introduce ISA v1.6.1 feature 2015-05-22 17:02:33 +02:00
cpu.h target-tricore: introduce ISA v1.6.1 feature 2015-05-22 17:02:33 +02:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00
op_helper.c target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00
translate.c target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00