mirror of https://gitee.com/openkylin/qemu.git
367 lines
10 KiB
C
367 lines
10 KiB
C
/* cris.h -- Header file for CRIS opcode and register tables.
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Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
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Contributed by Axis Communications AB, Lund, Sweden.
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Originally written for GAS 1.38.1 by Mikael Asker.
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Updated, BFDized and GNUified by Hans-Peter Nilsson.
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This file is part of GAS, GDB and the GNU binutils.
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GAS, GDB, and GNU binutils is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2, or (at your
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option) any later version.
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GAS, GDB, and GNU binutils are distributed in the hope that they will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef __CRIS_H_INCLUDED_
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#define __CRIS_H_INCLUDED_
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#if !defined(__STDC__) && !defined(const)
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#define const
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#endif
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/* Registers. */
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#define MAX_REG (15)
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#define REG_SP (14)
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#define REG_PC (15)
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/* CPU version control of disassembly and assembly of instructions.
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May affect how the instruction is assembled, at least the size of
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immediate operands. */
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enum cris_insn_version_usage
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{
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/* Any version. */
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cris_ver_version_all=0,
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/* Indeterminate (intended for disassembly only, or obsolete). */
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cris_ver_warning,
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/* Only for v0..3 (Etrax 1..4). */
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cris_ver_v0_3,
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/* Only for v3 or higher (ETRAX 4 and beyond). */
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cris_ver_v3p,
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/* Only for v8 (Etrax 100). */
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cris_ver_v8,
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/* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
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cris_ver_v8p,
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/* Only for v0..10. FIXME: Not sure what to do with this. */
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cris_ver_sim_v0_10,
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/* Only for v0..10. */
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cris_ver_v0_10,
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/* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
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cris_ver_v3_10,
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/* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
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cris_ver_v8_10,
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/* Only for v10 (ETRAX 100 LX) and same series. */
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cris_ver_v10,
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/* Only for v10 (ETRAX 100 LX) and same series. */
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cris_ver_v10p,
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/* Only for v32 or higher (codename GUINNESS).
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Of course some or all these of may change to cris_ver_v32p if/when
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there's a new revision. */
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cris_ver_v32p
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};
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/* Special registers. */
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struct cris_spec_reg
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{
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const char *const name;
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unsigned int number;
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/* The size of the register. */
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unsigned int reg_size;
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/* What CPU version the special register of that name is implemented
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in. If cris_ver_warning, emit an unimplemented-warning. */
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enum cris_insn_version_usage applicable_version;
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/* There might be a specific warning for using a special register
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here. */
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const char *const warning;
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};
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extern const struct cris_spec_reg cris_spec_regs[];
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/* Support registers (kind of special too, but not named as such). */
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struct cris_support_reg
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{
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const char *const name;
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unsigned int number;
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};
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extern const struct cris_support_reg cris_support_regs[];
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struct cris_cond15
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{
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/* The name of the condition. */
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const char *const name;
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/* What CPU version this condition name applies to. */
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enum cris_insn_version_usage applicable_version;
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};
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extern const struct cris_cond15 cris_conds15[];
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/* Opcode-dependent constants. */
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#define AUTOINCR_BIT (0x04)
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/* Prefixes. */
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#define BDAP_QUICK_OPCODE (0x0100)
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#define BDAP_QUICK_Z_BITS (0x0e00)
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#define BIAP_OPCODE (0x0540)
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#define BIAP_Z_BITS (0x0a80)
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#define DIP_OPCODE (0x0970)
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#define DIP_Z_BITS (0xf280)
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#define BDAP_INDIR_LOW (0x40)
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#define BDAP_INDIR_LOW_Z (0x80)
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#define BDAP_INDIR_HIGH (0x09)
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#define BDAP_INDIR_HIGH_Z (0x02)
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#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
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#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
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#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC)
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#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
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/* No prefix must have this code for its "match" bits in the
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opcode-table. "BCC .+2" will do nicely. */
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#define NO_CRIS_PREFIX 0
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/* Definitions for condition codes. */
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#define CC_CC 0x0
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#define CC_HS 0x0
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#define CC_CS 0x1
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#define CC_LO 0x1
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#define CC_NE 0x2
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#define CC_EQ 0x3
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#define CC_VC 0x4
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#define CC_VS 0x5
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#define CC_PL 0x6
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#define CC_MI 0x7
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#define CC_LS 0x8
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#define CC_HI 0x9
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#define CC_GE 0xA
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#define CC_LT 0xB
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#define CC_GT 0xC
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#define CC_LE 0xD
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#define CC_A 0xE
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#define CC_EXT 0xF
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/* A table of strings "cc", "cs"... indexed with condition code
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values as above. */
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extern const char *const cris_cc_strings[];
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/* Bcc quick. */
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#define BRANCH_QUICK_LOW (0)
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#define BRANCH_QUICK_HIGH (0)
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#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
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#define BRANCH_QUICK_Z_BITS (0x0F00)
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/* BA quick. */
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#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
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#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
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/* Bcc [PC+]. */
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#define BRANCH_PC_LOW (0xFF)
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#define BRANCH_INCR_HIGH (0x0D)
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#define BA_PC_INCR_OPCODE \
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((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
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/* Jump. */
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/* Note that old versions generated special register 8 (in high bits)
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and not-that-old versions recognized it as a jump-instruction.
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That opcode now belongs to JUMPU. */
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#define JUMP_INDIR_OPCODE (0x0930)
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#define JUMP_INDIR_Z_BITS (0xf2c0)
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#define JUMP_PC_INCR_OPCODE \
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(JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
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#define MOVE_M_TO_PREG_OPCODE 0x0a30
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#define MOVE_M_TO_PREG_ZBITS 0x01c0
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/* BDAP.D N,PC. */
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#define MOVE_PC_INCR_OPCODE_PREFIX \
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(((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
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#define MOVE_PC_INCR_OPCODE_SUFFIX \
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(MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
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#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
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/* BA DWORD (V32). */
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#define BA_DWORD_OPCODE (0x0EBF)
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/* Nop. */
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#define NOP_OPCODE (0x050F)
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#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
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#define NOP_OPCODE_V32 (0x05B0)
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#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
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/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
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registers or flags. Unfortunately shuts off interrupts for one cycle
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for < v32, but there doesn't seem to be any alternative without that
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effect. */
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#define NOP_OPCODE_COMMON (0x630)
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#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
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/* LAPC.D */
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#define LAPC_DWORD_OPCODE (0x0D7F)
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#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
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/* Structure of an opcode table entry. */
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enum cris_imm_oprnd_size_type
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{
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/* No size is applicable. */
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SIZE_NONE,
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/* Always 32 bits. */
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SIZE_FIX_32,
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/* Indicated by size of special register. */
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SIZE_SPEC_REG,
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/* Indicated by size field, signed. */
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SIZE_FIELD_SIGNED,
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/* Indicated by size field, unsigned. */
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SIZE_FIELD_UNSIGNED,
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/* Indicated by size field, no sign implied. */
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SIZE_FIELD
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};
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/* For GDB. FIXME: Is this the best way to handle opcode
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interpretation? */
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enum cris_op_type
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{
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cris_not_implemented_op = 0,
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cris_abs_op,
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cris_addi_op,
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cris_asr_op,
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cris_asrq_op,
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cris_ax_ei_setf_op,
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cris_bdap_prefix,
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cris_biap_prefix,
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cris_break_op,
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cris_btst_nop_op,
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cris_clearf_di_op,
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cris_dip_prefix,
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cris_dstep_logshift_mstep_neg_not_op,
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cris_eight_bit_offset_branch_op,
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cris_move_mem_to_reg_movem_op,
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cris_move_reg_to_mem_movem_op,
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cris_move_to_preg_op,
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cris_muls_op,
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cris_mulu_op,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op,
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cris_none_reg_mode_clear_test_op,
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cris_none_reg_mode_jump_op,
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cris_none_reg_mode_move_from_preg_op,
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cris_quick_mode_add_sub_op,
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cris_quick_mode_and_cmp_move_or_op,
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cris_quick_mode_bdap_prefix,
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cris_reg_mode_add_sub_cmp_and_or_move_op,
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cris_reg_mode_clear_op,
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cris_reg_mode_jump_op,
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cris_reg_mode_move_from_preg_op,
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cris_reg_mode_test_op,
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cris_scc_op,
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cris_sixteen_bit_offset_branch_op,
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cris_three_operand_add_sub_cmp_and_or_op,
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cris_three_operand_bound_op,
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cris_two_operand_bound_op,
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cris_xor_op
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};
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struct cris_opcode
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{
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/* The name of the insn. */
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const char *name;
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/* Bits that must be 1 for a match. */
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unsigned int match;
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/* Bits that must be 0 for a match. */
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unsigned int lose;
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/* See the table in "opcodes/cris-opc.c". */
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const char *args;
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/* Nonzero if this is a delayed branch instruction. */
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char delayed;
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/* Size of immediate operands. */
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enum cris_imm_oprnd_size_type imm_oprnd_size;
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/* Indicates which version this insn was first implemented in. */
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enum cris_insn_version_usage applicable_version;
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/* What kind of operation this is. */
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enum cris_op_type op;
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};
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extern const struct cris_opcode cris_opcodes[];
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/* These macros are for the target-specific flags in disassemble_info
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used at disassembly. */
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/* This insn accesses memory. This flag is more trustworthy than
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checking insn_type for "dis_dref" which does not work for
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e.g. "JSR [foo]". */
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#define CRIS_DIS_FLAG_MEMREF (1 << 0)
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/* The "target" field holds a register number. */
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#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
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/* The "target2" field holds a register number; add it to "target". */
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#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
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/* Yet another add-on: the register in "target2" must be multiplied
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by 2 before adding to "target". */
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#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
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/* Yet another add-on: the register in "target2" must be multiplied
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by 4 (mutually exclusive with .._MULT2). */
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#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
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/* The register in "target2" is an indirect memory reference (of the
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register there), add to "target". Assumed size is dword (mutually
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exclusive with .._MULT[24]). */
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#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
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/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
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sign-extended before adding to "target". */
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#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
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/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
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sign-extended before adding to "target". */
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#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
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#endif /* __CRIS_H_INCLUDED_ */
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/*
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* Local variables:
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* eval: (c-set-style "gnu")
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* indent-tabs-mode: t
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* End:
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*/
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