qemu/target/riscv
Dayeol Lee 4a9b31b82b
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer, which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.

Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-30 11:04:28 -07:00
..
Makefile.objs RISC-V: Move non-ops from op_helper to cpu_helper 2018-10-17 13:02:14 -07:00
cpu.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu.h RISC-V: Allow setting and clearing multiple irqs 2018-10-17 13:02:09 -07:00
cpu_bits.h RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu_helper.c RISC-V: Move non-ops from op_helper to cpu_helper 2018-10-17 13:02:14 -07:00
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c target/riscv: Remove floatX_maybe_silence_nan from conversions 2018-05-17 15:27:15 -07:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
pmp.c target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 2018-10-30 11:04:28 -07:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c target/riscv: call gen_goto_tb on DISAS_TOO_MANY 2018-09-05 09:58:38 -07:00