mirror of https://gitee.com/openkylin/qemu.git
636 lines
22 KiB
C
636 lines
22 KiB
C
/*
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* pcie.c
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pcie_regs.h"
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#include "qemu/range.h"
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#include "qapi/qmp/qerror.h"
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//#define DEBUG_PCIE
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#ifdef DEBUG_PCIE
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# define PCIE_DPRINTF(fmt, ...) \
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fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
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#else
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# define PCIE_DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define PCIE_DEV_PRINTF(dev, fmt, ...) \
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PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
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/***************************************************************************
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* pci express capability helper functions
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*/
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int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
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{
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int pos;
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uint8_t *exp_cap;
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assert(pci_is_express(dev));
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pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
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PCI_EXP_VER2_SIZEOF);
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if (pos < 0) {
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return pos;
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}
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dev->exp.exp_cap = pos;
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exp_cap = dev->config + pos;
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/* capability register
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interrupt message number defaults to 0 */
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pci_set_word(exp_cap + PCI_EXP_FLAGS,
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((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
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PCI_EXP_FLAGS_VER2);
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/* device capability register
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* table 7-12:
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* roll based error reporting bit must be set by all
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* Functions conforming to the ECN, PCI Express Base
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* Specification, Revision 1.1., or subsequent PCI Express Base
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* Specification revisions.
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*/
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pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
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pci_set_long(exp_cap + PCI_EXP_LNKCAP,
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(port << PCI_EXP_LNKCAP_PN_SHIFT) |
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PCI_EXP_LNKCAP_ASPMS_0S |
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PCI_EXP_LNK_MLW_1 |
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PCI_EXP_LNK_LS_25);
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pci_set_word(exp_cap + PCI_EXP_LNKSTA,
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PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
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pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
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PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
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pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
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return pos;
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}
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int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
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{
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uint8_t type = PCI_EXP_TYPE_ENDPOINT;
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/*
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* Windows guests will report Code 10, device cannot start, if
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* a regular Endpoint type is exposed on a root complex. These
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* should instead be Root Complex Integrated Endpoints.
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*/
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if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
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type = PCI_EXP_TYPE_RC_END;
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}
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return pcie_cap_init(dev, offset, type, 0);
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}
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void pcie_cap_exit(PCIDevice *dev)
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{
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pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
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}
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uint8_t pcie_cap_get_type(const PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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assert(pos > 0);
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return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
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PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
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}
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/* MSI/MSI-X */
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/* pci express interrupt message number */
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/* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
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void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
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{
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uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
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assert(vector < 32);
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
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vector << PCI_EXP_FLAGS_IRQ_SHIFT);
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}
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uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
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{
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return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
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PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
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}
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void pcie_cap_deverr_init(PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
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PCI_EXP_DEVCAP_RBER);
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pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
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pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
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PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
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PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
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}
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void pcie_cap_deverr_reset(PCIDevice *dev)
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{
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uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
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pci_long_test_and_clear_mask(devctl,
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PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
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PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
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}
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static void hotplug_event_update_event_status(PCIDevice *dev)
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{
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uint32_t pos = dev->exp.exp_cap;
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uint8_t *exp_cap = dev->config + pos;
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uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
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dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
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(sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
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}
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static void hotplug_event_notify(PCIDevice *dev)
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{
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bool prev = dev->exp.hpev_notified;
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hotplug_event_update_event_status(dev);
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if (prev == dev->exp.hpev_notified) {
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return;
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}
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/* Note: the logic above does not take into account whether interrupts
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* are masked. The result is that interrupt will be sent when it is
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* subsequently unmasked. This appears to be legal: Section 6.7.3.4:
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* The Port may optionally send an MSI when there are hot-plug events that
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* occur while interrupt generation is disabled, and interrupt generation is
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* subsequently enabled. */
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if (msix_enabled(dev)) {
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msix_notify(dev, pcie_cap_flags_get_vector(dev));
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} else if (msi_enabled(dev)) {
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msi_notify(dev, pcie_cap_flags_get_vector(dev));
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} else {
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pci_set_irq(dev, dev->exp.hpev_notified);
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}
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}
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static void hotplug_event_clear(PCIDevice *dev)
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{
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hotplug_event_update_event_status(dev);
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if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
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pci_irq_deassert(dev);
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}
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}
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/*
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* A PCI Express Hot-Plug Event has occurred, so update slot status register
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* and notify OS of the event if necessary.
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*
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* 6.7.3 PCI Express Hot-Plug Events
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* 6.7.3.4 Software Notification of Hot-Plug Events
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*/
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static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
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{
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/* Minor optimization: if nothing changed - no event is needed. */
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if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
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PCI_EXP_SLTSTA, event)) {
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return;
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}
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hotplug_event_notify(dev);
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}
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static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev,
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DeviceState *dev,
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uint8_t **exp_cap, Error **errp)
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{
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*exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
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uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA);
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PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
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if (sltsta & PCI_EXP_SLTSTA_EIS) {
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/* the slot is electromechanically locked.
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* This error is propagated up to qdev and then to HMP/QMP.
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*/
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error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
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}
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}
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void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp)
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{
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uint8_t *exp_cap;
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
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/* Don't send event when device is enabled during qemu machine creation:
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* it is present on boot, no hotplug event is necessary. We do send an
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* event when the device is disabled later. */
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if (!dev->hotplugged) {
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_PDS);
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return;
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}
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/* TODO: multifunction hot-plug.
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* Right now, only a device of function = 0 is allowed to be
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* hot plugged/unplugged.
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*/
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assert(PCI_FUNC(pci_dev->devfn) == 0);
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_PDS);
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pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
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PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
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}
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void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp)
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{
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uint8_t *exp_cap;
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pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
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pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
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}
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/* pci express slot for pci express root/downstream port
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PCI express capability slot registers */
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void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
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{
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uint32_t pos = dev->exp.exp_cap;
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pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
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PCI_EXP_FLAGS_SLOT);
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pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
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~PCI_EXP_SLTCAP_PSN);
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
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(slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
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PCI_EXP_SLTCAP_EIP |
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PCI_EXP_SLTCAP_HPS |
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PCI_EXP_SLTCAP_HPC |
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PCI_EXP_SLTCAP_PIP |
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PCI_EXP_SLTCAP_AIP |
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PCI_EXP_SLTCAP_ABP);
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if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
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PCI_EXP_SLTCAP_PCP);
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pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PCC);
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pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PCC);
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}
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pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PIC |
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PCI_EXP_SLTCTL_AIC);
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pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PIC_OFF |
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PCI_EXP_SLTCTL_AIC_OFF);
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pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PIC |
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PCI_EXP_SLTCTL_AIC |
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PCI_EXP_SLTCTL_HPIE |
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PCI_EXP_SLTCTL_CCIE |
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PCI_EXP_SLTCTL_PDCE |
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PCI_EXP_SLTCTL_ABPE);
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/* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
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* make the bit writable here in order to detect 1b is written.
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* pcie_cap_slot_write_config() test-and-clear the bit, so
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* this bit always returns 0 to the guest.
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*/
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pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_EIC);
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pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
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PCI_EXP_HP_EV_SUPPORTED);
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dev->exp.hpev_notified = false;
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qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
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DEVICE(dev), NULL);
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}
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void pcie_cap_slot_reset(PCIDevice *dev)
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{
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uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
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uint8_t port_type = pcie_cap_get_type(dev);
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assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
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port_type == PCI_EXP_TYPE_ROOT_PORT);
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PCIE_DEV_PRINTF(dev, "reset\n");
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_EIC |
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PCI_EXP_SLTCTL_PIC |
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PCI_EXP_SLTCTL_AIC |
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PCI_EXP_SLTCTL_HPIE |
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PCI_EXP_SLTCTL_CCIE |
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PCI_EXP_SLTCTL_PDCE |
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PCI_EXP_SLTCTL_ABPE);
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_AIC_OFF);
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if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
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/* Downstream ports enforce device number 0. */
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bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
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uint16_t pic;
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if (populated) {
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PCC);
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} else {
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_PCC);
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}
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pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
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}
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_EIS |/* on reset,
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the lock is released */
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PCI_EXP_SLTSTA_CC |
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PCI_EXP_SLTSTA_PDC |
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PCI_EXP_SLTSTA_ABP);
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hotplug_event_update_event_status(dev);
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}
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static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
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{
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object_unparent(OBJECT(dev));
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}
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void pcie_cap_slot_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len)
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{
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uint32_t pos = dev->exp.exp_cap;
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uint8_t *exp_cap = dev->config + pos;
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uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
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if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
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hotplug_event_clear(dev);
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}
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if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
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return;
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}
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if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
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PCI_EXP_SLTCTL_EIC)) {
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sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
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pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
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PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
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"sltsta -> 0x%02"PRIx16"\n",
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sltsta);
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}
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/*
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* If the slot is polulated, power indicator is off and power
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* controller is off, it is safe to detach the devices.
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*/
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if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
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((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
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PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
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pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
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pcie_unplug_device, NULL);
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pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_PDS);
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pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_PDC);
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}
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hotplug_event_notify(dev);
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/*
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* 6.7.3.2 Command Completed Events
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*
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* Software issues a command to a hot-plug capable Downstream Port by
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* issuing a write transaction that targets any portion of the Port’s Slot
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* Control register. A single write to the Slot Control register is
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* considered to be a single command, even if the write affects more than
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* one field in the Slot Control register. In response to this transaction,
|
||
* the Port must carry out the requested actions and then set the
|
||
* associated status field for the command completed event. */
|
||
|
||
/* Real hardware might take a while to complete requested command because
|
||
* physical movement would be involved like locking the electromechanical
|
||
* lock. However in our case, command is completed instantaneously above,
|
||
* so send a command completion event right now.
|
||
*/
|
||
pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
|
||
}
|
||
|
||
int pcie_cap_slot_post_load(void *opaque, int version_id)
|
||
{
|
||
PCIDevice *dev = opaque;
|
||
hotplug_event_update_event_status(dev);
|
||
return 0;
|
||
}
|
||
|
||
void pcie_cap_slot_push_attention_button(PCIDevice *dev)
|
||
{
|
||
pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
|
||
}
|
||
|
||
/* root control/capabilities/status. PME isn't emulated for now */
|
||
void pcie_cap_root_init(PCIDevice *dev)
|
||
{
|
||
pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
|
||
PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
|
||
PCI_EXP_RTCTL_SEFEE);
|
||
}
|
||
|
||
void pcie_cap_root_reset(PCIDevice *dev)
|
||
{
|
||
pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
|
||
}
|
||
|
||
/* function level reset(FLR) */
|
||
void pcie_cap_flr_init(PCIDevice *dev)
|
||
{
|
||
pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
|
||
PCI_EXP_DEVCAP_FLR);
|
||
|
||
/* Although reading BCR_FLR returns always 0,
|
||
* the bit is made writable here in order to detect the 1b is written
|
||
* pcie_cap_flr_write_config() test-and-clear the bit, so
|
||
* this bit always returns 0 to the guest.
|
||
*/
|
||
pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
|
||
PCI_EXP_DEVCTL_BCR_FLR);
|
||
}
|
||
|
||
void pcie_cap_flr_write_config(PCIDevice *dev,
|
||
uint32_t addr, uint32_t val, int len)
|
||
{
|
||
uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
|
||
if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
|
||
/* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
|
||
so the handler can detect FLR by looking at this bit. */
|
||
pci_device_reset(dev);
|
||
pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
|
||
}
|
||
}
|
||
|
||
/* Alternative Routing-ID Interpretation (ARI)
|
||
* forwarding support for root and downstream ports
|
||
*/
|
||
void pcie_cap_arifwd_init(PCIDevice *dev)
|
||
{
|
||
uint32_t pos = dev->exp.exp_cap;
|
||
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
|
||
PCI_EXP_DEVCAP2_ARI);
|
||
pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
|
||
PCI_EXP_DEVCTL2_ARI);
|
||
}
|
||
|
||
void pcie_cap_arifwd_reset(PCIDevice *dev)
|
||
{
|
||
uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
|
||
pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
|
||
}
|
||
|
||
bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
|
||
{
|
||
if (!pci_is_express(dev)) {
|
||
return false;
|
||
}
|
||
if (!dev->exp.exp_cap) {
|
||
return false;
|
||
}
|
||
|
||
return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
|
||
PCI_EXP_DEVCTL2_ARI;
|
||
}
|
||
|
||
/**************************************************************************
|
||
* pci express extended capability list management functions
|
||
* uint16_t ext_cap_id (16 bit)
|
||
* uint8_t cap_ver (4 bit)
|
||
* uint16_t cap_offset (12 bit)
|
||
* uint16_t ext_cap_size
|
||
*/
|
||
|
||
static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
|
||
uint16_t *prev_p)
|
||
{
|
||
uint16_t prev = 0;
|
||
uint16_t next;
|
||
uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
|
||
|
||
if (!header) {
|
||
/* no extended capability */
|
||
next = 0;
|
||
goto out;
|
||
}
|
||
for (next = PCI_CONFIG_SPACE_SIZE; next;
|
||
prev = next, next = PCI_EXT_CAP_NEXT(header)) {
|
||
|
||
assert(next >= PCI_CONFIG_SPACE_SIZE);
|
||
assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
|
||
|
||
header = pci_get_long(dev->config + next);
|
||
if (PCI_EXT_CAP_ID(header) == cap_id) {
|
||
break;
|
||
}
|
||
}
|
||
|
||
out:
|
||
if (prev_p) {
|
||
*prev_p = prev;
|
||
}
|
||
return next;
|
||
}
|
||
|
||
uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
|
||
{
|
||
return pcie_find_capability_list(dev, cap_id, NULL);
|
||
}
|
||
|
||
static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
|
||
{
|
||
uint32_t header = pci_get_long(dev->config + pos);
|
||
assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
|
||
header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
|
||
((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
|
||
pci_set_long(dev->config + pos, header);
|
||
}
|
||
|
||
/*
|
||
* caller must supply valid (offset, size) * such that the range shouldn't
|
||
* overlap with other capability or other registers.
|
||
* This function doesn't check it.
|
||
*/
|
||
void pcie_add_capability(PCIDevice *dev,
|
||
uint16_t cap_id, uint8_t cap_ver,
|
||
uint16_t offset, uint16_t size)
|
||
{
|
||
uint32_t header;
|
||
uint16_t next;
|
||
|
||
assert(offset >= PCI_CONFIG_SPACE_SIZE);
|
||
assert(offset < offset + size);
|
||
assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
|
||
assert(size >= 8);
|
||
assert(pci_is_express(dev));
|
||
|
||
if (offset == PCI_CONFIG_SPACE_SIZE) {
|
||
header = pci_get_long(dev->config + offset);
|
||
next = PCI_EXT_CAP_NEXT(header);
|
||
} else {
|
||
uint16_t prev;
|
||
|
||
/* 0 is reserved cap id. use internally to find the last capability
|
||
in the linked list */
|
||
next = pcie_find_capability_list(dev, 0, &prev);
|
||
|
||
assert(prev >= PCI_CONFIG_SPACE_SIZE);
|
||
assert(next == 0);
|
||
pcie_ext_cap_set_next(dev, prev, offset);
|
||
}
|
||
pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
|
||
|
||
/* Make capability read-only by default */
|
||
memset(dev->wmask + offset, 0, size);
|
||
memset(dev->w1cmask + offset, 0, size);
|
||
/* Check capability by default */
|
||
memset(dev->cmask + offset, 0xFF, size);
|
||
}
|
||
|
||
/**************************************************************************
|
||
* pci express extended capability helper functions
|
||
*/
|
||
|
||
/* ARI */
|
||
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
|
||
{
|
||
pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
|
||
offset, PCI_ARI_SIZEOF);
|
||
pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
|
||
}
|