mirror of https://gitee.com/openkylin/qemu.git
128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* i.MX7 GPCv2 block emulation code
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/intc/imx_gpcv2.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
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#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
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#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
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#define PCIE_PHY_SW_Pxx_REQ BIT(1)
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#define MIPI_PHY_SW_Pxx_REQ BIT(0)
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static void imx_gpcv2_reset(DeviceState *dev)
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{
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IMXGPCv2State *s = IMX_GPCV2(dev);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static uint64_t imx_gpcv2_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXGPCv2State *s = opaque;
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return s->regs[offset / sizeof(uint32_t)];
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}
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static void imx_gpcv2_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXGPCv2State *s = opaque;
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const size_t idx = offset / sizeof(uint32_t);
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s->regs[idx] = value;
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/*
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* Real HW will clear those bits once as a way to indicate that
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* power up request is complete
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*/
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if (offset == GPC_PU_PGC_SW_PUP_REQ ||
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offset == GPC_PU_PGC_SW_PDN_REQ) {
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s->regs[idx] &= ~(USB_HSIC_PHY_SW_Pxx_REQ |
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USB_OTG2_PHY_SW_Pxx_REQ |
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USB_OTG1_PHY_SW_Pxx_REQ |
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PCIE_PHY_SW_Pxx_REQ |
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MIPI_PHY_SW_Pxx_REQ);
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}
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}
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static const struct MemoryRegionOps imx_gpcv2_ops = {
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.read = imx_gpcv2_read,
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.write = imx_gpcv2_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx_gpcv2_init(Object *obj)
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{
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMXGPCv2State *s = IMX_GPCV2(obj);
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memory_region_init_io(&s->iomem,
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obj,
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&imx_gpcv2_ops,
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s,
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TYPE_IMX_GPCV2 ".iomem",
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sizeof(s->regs));
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sysbus_init_mmio(sd, &s->iomem);
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}
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static const VMStateDescription vmstate_imx_gpcv2 = {
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.name = TYPE_IMX_GPCV2,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, IMXGPCv2State, GPC_NUM),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_gpcv2_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = imx_gpcv2_reset;
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dc->vmsd = &vmstate_imx_gpcv2;
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dc->desc = "i.MX GPCv2 Module";
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}
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static const TypeInfo imx_gpcv2_info = {
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.name = TYPE_IMX_GPCV2,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXGPCv2State),
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.instance_init = imx_gpcv2_init,
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.class_init = imx_gpcv2_class_init,
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};
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static void imx_gpcv2_register_type(void)
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{
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type_register_static(&imx_gpcv2_info);
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}
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type_init(imx_gpcv2_register_type)
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