mirror of https://gitee.com/openkylin/qemu.git
999 lines
31 KiB
C
999 lines
31 KiB
C
/*
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* ARM Nested Vectored Interrupt Controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*
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* The ARMv7M System controller is fairly tightly tied in with the
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* NVIC. Much of that is also implemented here.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "hw/arm/arm.h"
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#include "hw/arm/armv7m_nvic.h"
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#include "target/arm/cpu.h"
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#include "qemu/log.h"
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#include "trace.h"
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/* IRQ number counting:
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*
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* the num-irq property counts the number of external IRQ lines
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*
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* NVICState::num_irq counts the total number of exceptions
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* (external IRQs, the 15 internal exceptions including reset,
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* and one for the unused exception number 0).
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*
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* NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
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*
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* NVIC_MAX_VECTORS is the highest permitted number of exceptions.
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*
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* Iterating through all exceptions should typically be done with
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* for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
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*
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* The external qemu_irq lines are the NVIC's external IRQ lines,
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* so line 0 is exception 16.
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*
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* In the terminology of the architecture manual, "interrupts" are
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* a subcategory of exception referring to the external interrupts
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* (which are exception numbers NVIC_FIRST_IRQ and upward).
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* For historical reasons QEMU tends to use "interrupt" and
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* "exception" more or less interchangeably.
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*/
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#define NVIC_FIRST_IRQ 16
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#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
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/* Effective running priority of the CPU when no exception is active
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* (higher than the highest possible priority value)
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*/
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#define NVIC_NOEXC_PRIO 0x100
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static const uint8_t nvic_id[] = {
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0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
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};
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static int nvic_pending_prio(NVICState *s)
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{
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/* return the priority of the current pending interrupt,
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* or NVIC_NOEXC_PRIO if no interrupt is pending
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*/
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return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
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}
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/* Return the value of the ISCR RETTOBASE bit:
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* 1 if there is exactly one active exception
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* 0 if there is more than one active exception
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* UNKNOWN if there are no active exceptions (we choose 1,
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* which matches the choice Cortex-M3 is documented as making).
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*
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* NB: some versions of the documentation talk about this
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* counting "active exceptions other than the one shown by IPSR";
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* this is only different in the obscure corner case where guest
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* code has manually deactivated an exception and is about
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* to fail an exception-return integrity check. The definition
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* above is the one from the v8M ARM ARM and is also in line
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* with the behaviour documented for the Cortex-M3.
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*/
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static bool nvic_rettobase(NVICState *s)
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{
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int irq, nhand = 0;
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for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
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if (s->vectors[irq].active) {
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nhand++;
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if (nhand == 2) {
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return 0;
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}
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}
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}
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return 1;
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}
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/* Return the value of the ISCR ISRPENDING bit:
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* 1 if an external interrupt is pending
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* 0 if no external interrupt is pending
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*/
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static bool nvic_isrpending(NVICState *s)
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{
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int irq;
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/* We can shortcut if the highest priority pending interrupt
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* happens to be external or if there is nothing pending.
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*/
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if (s->vectpending > NVIC_FIRST_IRQ) {
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return true;
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}
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if (s->vectpending == 0) {
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return false;
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}
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for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
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if (s->vectors[irq].pending) {
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return true;
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}
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}
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return false;
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}
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/* Return a mask word which clears the subpriority bits from
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* a priority value for an M-profile exception, leaving only
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* the group priority.
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*/
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static inline uint32_t nvic_gprio_mask(NVICState *s)
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{
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return ~0U << (s->prigroup + 1);
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}
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/* Recompute vectpending and exception_prio */
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static void nvic_recompute_state(NVICState *s)
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{
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int i;
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int pend_prio = NVIC_NOEXC_PRIO;
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int active_prio = NVIC_NOEXC_PRIO;
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int pend_irq = 0;
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for (i = 1; i < s->num_irq; i++) {
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VecInfo *vec = &s->vectors[i];
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if (vec->enabled && vec->pending && vec->prio < pend_prio) {
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pend_prio = vec->prio;
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pend_irq = i;
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}
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if (vec->active && vec->prio < active_prio) {
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active_prio = vec->prio;
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}
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}
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s->vectpending = pend_irq;
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s->exception_prio = active_prio & nvic_gprio_mask(s);
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trace_nvic_recompute_state(s->vectpending, s->exception_prio);
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}
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/* Return the current execution priority of the CPU
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* (equivalent to the pseudocode ExecutionPriority function).
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* This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
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*/
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static inline int nvic_exec_prio(NVICState *s)
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{
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CPUARMState *env = &s->cpu->env;
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int running;
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if (env->daif & PSTATE_F) { /* FAULTMASK */
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running = -1;
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} else if (env->daif & PSTATE_I) { /* PRIMASK */
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running = 0;
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} else if (env->v7m.basepri > 0) {
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running = env->v7m.basepri & nvic_gprio_mask(s);
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} else {
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running = NVIC_NOEXC_PRIO; /* lower than any possible priority */
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}
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/* consider priority of active handler */
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return MIN(running, s->exception_prio);
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}
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bool armv7m_nvic_can_take_pending_exception(void *opaque)
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{
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NVICState *s = opaque;
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return nvic_exec_prio(s) > nvic_pending_prio(s);
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}
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/* caller must call nvic_irq_update() after this */
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static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
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{
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assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
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assert(irq < s->num_irq);
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s->vectors[irq].prio = prio;
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trace_nvic_set_prio(irq, prio);
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}
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/* Recompute state and assert irq line accordingly.
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* Must be called after changes to:
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* vec->active, vec->enabled, vec->pending or vec->prio for any vector
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* prigroup
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*/
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static void nvic_irq_update(NVICState *s)
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{
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int lvl;
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int pend_prio;
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nvic_recompute_state(s);
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pend_prio = nvic_pending_prio(s);
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/* Raise NVIC output if this IRQ would be taken, except that we
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* ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
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* will be checked for in arm_v7m_cpu_exec_interrupt()); changes
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* to those CPU registers don't cause us to recalculate the NVIC
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* pending info.
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*/
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lvl = (pend_prio < s->exception_prio);
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trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
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qemu_set_irq(s->excpout, lvl);
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}
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static void armv7m_nvic_clear_pending(void *opaque, int irq)
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{
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NVICState *s = (NVICState *)opaque;
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VecInfo *vec;
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assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
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vec = &s->vectors[irq];
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trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
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if (vec->pending) {
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vec->pending = 0;
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nvic_irq_update(s);
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}
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}
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void armv7m_nvic_set_pending(void *opaque, int irq)
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{
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NVICState *s = (NVICState *)opaque;
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VecInfo *vec;
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assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
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vec = &s->vectors[irq];
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trace_nvic_set_pending(irq, vec->enabled, vec->prio);
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if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
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/* If a synchronous exception is pending then it may be
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* escalated to HardFault if:
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* * it is equal or lower priority to current execution
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* * it is disabled
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* (ie we need to take it immediately but we can't do so).
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* Asynchronous exceptions (and interrupts) simply remain pending.
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*
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* For QEMU, we don't have any imprecise (asynchronous) faults,
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* so we can assume that PREFETCH_ABORT and DATA_ABORT are always
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* synchronous.
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* Debug exceptions are awkward because only Debug exceptions
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* resulting from the BKPT instruction should be escalated,
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* but we don't currently implement any Debug exceptions other
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* than those that result from BKPT, so we treat all debug exceptions
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* as needing escalation.
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*
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* This all means we can identify whether to escalate based only on
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* the exception number and don't (yet) need the caller to explicitly
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* tell us whether this exception is synchronous or not.
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*/
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int running = nvic_exec_prio(s);
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bool escalate = false;
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if (vec->prio >= running) {
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trace_nvic_escalate_prio(irq, vec->prio, running);
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escalate = true;
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} else if (!vec->enabled) {
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trace_nvic_escalate_disabled(irq);
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escalate = true;
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}
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if (escalate) {
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if (running < 0) {
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/* We want to escalate to HardFault but we can't take a
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* synchronous HardFault at this point either. This is a
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* Lockup condition due to a guest bug. We don't model
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* Lockup, so report via cpu_abort() instead.
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*/
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cpu_abort(&s->cpu->parent_obj,
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"Lockup: can't escalate %d to HardFault "
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"(current priority %d)\n", irq, running);
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}
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/* We can do the escalation, so we take HardFault instead */
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irq = ARMV7M_EXCP_HARD;
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vec = &s->vectors[irq];
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s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
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}
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}
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if (!vec->pending) {
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vec->pending = 1;
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nvic_irq_update(s);
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}
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}
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/* Make pending IRQ active. */
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void armv7m_nvic_acknowledge_irq(void *opaque)
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{
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NVICState *s = (NVICState *)opaque;
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CPUARMState *env = &s->cpu->env;
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const int pending = s->vectpending;
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const int running = nvic_exec_prio(s);
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int pendgroupprio;
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VecInfo *vec;
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assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
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vec = &s->vectors[pending];
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assert(vec->enabled);
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assert(vec->pending);
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pendgroupprio = vec->prio & nvic_gprio_mask(s);
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assert(pendgroupprio < running);
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trace_nvic_acknowledge_irq(pending, vec->prio);
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vec->active = 1;
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vec->pending = 0;
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env->v7m.exception = s->vectpending;
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nvic_irq_update(s);
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}
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int armv7m_nvic_complete_irq(void *opaque, int irq)
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{
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NVICState *s = (NVICState *)opaque;
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VecInfo *vec;
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int ret;
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assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
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vec = &s->vectors[irq];
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trace_nvic_complete_irq(irq);
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if (!vec->active) {
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/* Tell the caller this was an illegal exception return */
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return -1;
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}
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ret = nvic_rettobase(s);
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vec->active = 0;
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if (vec->level) {
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/* Re-pend the exception if it's still held high; only
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* happens for extenal IRQs
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*/
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assert(irq >= NVIC_FIRST_IRQ);
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vec->pending = 1;
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}
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nvic_irq_update(s);
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return ret;
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}
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/* callback when external interrupt line is changed */
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static void set_irq_level(void *opaque, int n, int level)
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{
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NVICState *s = opaque;
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VecInfo *vec;
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n += NVIC_FIRST_IRQ;
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assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
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trace_nvic_set_irq_level(n, level);
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/* The pending status of an external interrupt is
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* latched on rising edge and exception handler return.
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*
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* Pulsing the IRQ will always run the handler
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* once, and the handler will re-run until the
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* level is low when the handler completes.
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*/
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vec = &s->vectors[n];
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if (level != vec->level) {
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vec->level = level;
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if (level) {
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armv7m_nvic_set_pending(s, n);
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}
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}
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}
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static uint32_t nvic_readl(NVICState *s, uint32_t offset)
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{
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ARMCPU *cpu = s->cpu;
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uint32_t val;
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switch (offset) {
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case 4: /* Interrupt Control Type. */
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return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
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case 0xd00: /* CPUID Base. */
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return cpu->midr;
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case 0xd04: /* Interrupt Control State. */
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/* VECTACTIVE */
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val = cpu->env.v7m.exception;
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/* VECTPENDING */
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val |= (s->vectpending & 0xff) << 12;
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/* ISRPENDING - set if any external IRQ is pending */
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if (nvic_isrpending(s)) {
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val |= (1 << 22);
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}
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/* RETTOBASE - set if only one handler is active */
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if (nvic_rettobase(s)) {
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val |= (1 << 11);
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}
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/* PENDSTSET */
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if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
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val |= (1 << 26);
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}
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/* PENDSVSET */
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if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
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val |= (1 << 28);
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}
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/* NMIPENDSET */
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if (s->vectors[ARMV7M_EXCP_NMI].pending) {
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val |= (1 << 31);
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}
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/* ISRPREEMPT not implemented */
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return val;
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case 0xd08: /* Vector Table Offset. */
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return cpu->env.v7m.vecbase;
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case 0xd0c: /* Application Interrupt/Reset Control. */
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return 0xfa050000 | (s->prigroup << 8);
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case 0xd10: /* System Control. */
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/* TODO: Implement SLEEPONEXIT. */
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return 0;
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case 0xd14: /* Configuration Control. */
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return cpu->env.v7m.ccr;
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case 0xd24: /* System Handler Status. */
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val = 0;
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if (s->vectors[ARMV7M_EXCP_MEM].active) {
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val |= (1 << 0);
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}
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if (s->vectors[ARMV7M_EXCP_BUS].active) {
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val |= (1 << 1);
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}
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if (s->vectors[ARMV7M_EXCP_USAGE].active) {
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val |= (1 << 3);
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}
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if (s->vectors[ARMV7M_EXCP_SVC].active) {
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val |= (1 << 7);
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}
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if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
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val |= (1 << 8);
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}
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if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
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val |= (1 << 10);
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}
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if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
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val |= (1 << 11);
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}
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if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
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val |= (1 << 12);
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}
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if (s->vectors[ARMV7M_EXCP_MEM].pending) {
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val |= (1 << 13);
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}
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if (s->vectors[ARMV7M_EXCP_BUS].pending) {
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val |= (1 << 14);
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}
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if (s->vectors[ARMV7M_EXCP_SVC].pending) {
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val |= (1 << 15);
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}
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if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
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val |= (1 << 16);
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}
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if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
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val |= (1 << 17);
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}
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if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
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val |= (1 << 18);
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}
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return val;
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case 0xd28: /* Configurable Fault Status. */
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return cpu->env.v7m.cfsr;
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case 0xd2c: /* Hard Fault Status. */
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return cpu->env.v7m.hfsr;
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case 0xd30: /* Debug Fault Status. */
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return cpu->env.v7m.dfsr;
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case 0xd34: /* MMFAR MemManage Fault Address */
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return cpu->env.v7m.mmfar;
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case 0xd38: /* Bus Fault Address. */
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return cpu->env.v7m.bfar;
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case 0xd3c: /* Aux Fault Status. */
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/* TODO: Implement fault status registers. */
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qemu_log_mask(LOG_UNIMP,
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"Aux Fault status registers unimplemented\n");
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return 0;
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case 0xd40: /* PFR0. */
|
|
return 0x00000030;
|
|
case 0xd44: /* PRF1. */
|
|
return 0x00000200;
|
|
case 0xd48: /* DFR0. */
|
|
return 0x00100000;
|
|
case 0xd4c: /* AFR0. */
|
|
return 0x00000000;
|
|
case 0xd50: /* MMFR0. */
|
|
return 0x00000030;
|
|
case 0xd54: /* MMFR1. */
|
|
return 0x00000000;
|
|
case 0xd58: /* MMFR2. */
|
|
return 0x00000000;
|
|
case 0xd5c: /* MMFR3. */
|
|
return 0x00000000;
|
|
case 0xd60: /* ISAR0. */
|
|
return 0x01141110;
|
|
case 0xd64: /* ISAR1. */
|
|
return 0x02111000;
|
|
case 0xd68: /* ISAR2. */
|
|
return 0x21112231;
|
|
case 0xd6c: /* ISAR3. */
|
|
return 0x01111110;
|
|
case 0xd70: /* ISAR4. */
|
|
return 0x01310102;
|
|
/* TODO: Implement debug registers. */
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
|
|
{
|
|
ARMCPU *cpu = s->cpu;
|
|
|
|
switch (offset) {
|
|
case 0xd04: /* Interrupt Control State. */
|
|
if (value & (1 << 31)) {
|
|
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
|
|
}
|
|
if (value & (1 << 28)) {
|
|
armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
|
|
} else if (value & (1 << 27)) {
|
|
armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
|
|
}
|
|
if (value & (1 << 26)) {
|
|
armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
|
|
} else if (value & (1 << 25)) {
|
|
armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
|
|
}
|
|
break;
|
|
case 0xd08: /* Vector Table Offset. */
|
|
cpu->env.v7m.vecbase = value & 0xffffff80;
|
|
break;
|
|
case 0xd0c: /* Application Interrupt/Reset Control. */
|
|
if ((value >> 16) == 0x05fa) {
|
|
if (value & 4) {
|
|
qemu_irq_pulse(s->sysresetreq);
|
|
}
|
|
if (value & 2) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"Setting VECTCLRACTIVE when not in DEBUG mode "
|
|
"is UNPREDICTABLE\n");
|
|
}
|
|
if (value & 1) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"Setting VECTRESET when not in DEBUG mode "
|
|
"is UNPREDICTABLE\n");
|
|
}
|
|
s->prigroup = extract32(value, 8, 3);
|
|
nvic_irq_update(s);
|
|
}
|
|
break;
|
|
case 0xd10: /* System Control. */
|
|
/* TODO: Implement control registers. */
|
|
qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n");
|
|
break;
|
|
case 0xd14: /* Configuration Control. */
|
|
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
|
|
value &= (R_V7M_CCR_STKALIGN_MASK |
|
|
R_V7M_CCR_BFHFNMIGN_MASK |
|
|
R_V7M_CCR_DIV_0_TRP_MASK |
|
|
R_V7M_CCR_UNALIGN_TRP_MASK |
|
|
R_V7M_CCR_USERSETMPEND_MASK |
|
|
R_V7M_CCR_NONBASETHRDENA_MASK);
|
|
|
|
cpu->env.v7m.ccr = value;
|
|
break;
|
|
case 0xd24: /* System Handler Control. */
|
|
s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
|
|
s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
|
|
s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
|
|
s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
|
|
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
|
|
s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
|
|
s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
|
|
s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
|
|
s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
|
|
s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
|
|
s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
|
|
s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
|
|
s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
|
|
s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
|
|
nvic_irq_update(s);
|
|
break;
|
|
case 0xd28: /* Configurable Fault Status. */
|
|
cpu->env.v7m.cfsr &= ~value; /* W1C */
|
|
break;
|
|
case 0xd2c: /* Hard Fault Status. */
|
|
cpu->env.v7m.hfsr &= ~value; /* W1C */
|
|
break;
|
|
case 0xd30: /* Debug Fault Status. */
|
|
cpu->env.v7m.dfsr &= ~value; /* W1C */
|
|
break;
|
|
case 0xd34: /* Mem Manage Address. */
|
|
cpu->env.v7m.mmfar = value;
|
|
return;
|
|
case 0xd38: /* Bus Fault Address. */
|
|
cpu->env.v7m.bfar = value;
|
|
return;
|
|
case 0xd3c: /* Aux Fault Status. */
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"NVIC: Aux fault status registers unimplemented\n");
|
|
break;
|
|
case 0xf00: /* Software Triggered Interrupt Register */
|
|
{
|
|
/* user mode can only write to STIR if CCR.USERSETMPEND permits it */
|
|
int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
|
|
if (excnum < s->num_irq &&
|
|
(arm_current_el(&cpu->env) ||
|
|
(cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
|
|
armv7m_nvic_set_pending(s, excnum);
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"NVIC: Bad write offset 0x%x\n", offset);
|
|
}
|
|
}
|
|
|
|
static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
NVICState *s = (NVICState *)opaque;
|
|
uint32_t offset = addr;
|
|
unsigned i, startvec, end;
|
|
uint32_t val;
|
|
|
|
switch (offset) {
|
|
/* reads of set and clear both return the status */
|
|
case 0x100 ... 0x13f: /* NVIC Set enable */
|
|
offset += 0x80;
|
|
/* fall through */
|
|
case 0x180 ... 0x1bf: /* NVIC Clear enable */
|
|
val = 0;
|
|
startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */
|
|
|
|
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
|
|
if (s->vectors[startvec + i].enabled) {
|
|
val |= (1 << i);
|
|
}
|
|
}
|
|
break;
|
|
case 0x200 ... 0x23f: /* NVIC Set pend */
|
|
offset += 0x80;
|
|
/* fall through */
|
|
case 0x280 ... 0x2bf: /* NVIC Clear pend */
|
|
val = 0;
|
|
startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */
|
|
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
|
|
if (s->vectors[startvec + i].pending) {
|
|
val |= (1 << i);
|
|
}
|
|
}
|
|
break;
|
|
case 0x300 ... 0x33f: /* NVIC Active */
|
|
val = 0;
|
|
startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */
|
|
|
|
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
|
|
if (s->vectors[startvec + i].active) {
|
|
val |= (1 << i);
|
|
}
|
|
}
|
|
break;
|
|
case 0x400 ... 0x5ef: /* NVIC Priority */
|
|
val = 0;
|
|
startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */
|
|
|
|
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
|
|
val |= s->vectors[startvec + i].prio << (8 * i);
|
|
}
|
|
break;
|
|
case 0xd18 ... 0xd23: /* System Handler Priority. */
|
|
val = 0;
|
|
for (i = 0; i < size; i++) {
|
|
val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
|
|
}
|
|
break;
|
|
case 0xfe0 ... 0xfff: /* ID. */
|
|
if (offset & 3) {
|
|
val = 0;
|
|
} else {
|
|
val = nvic_id[(offset - 0xfe0) >> 2];
|
|
}
|
|
break;
|
|
default:
|
|
if (size == 4) {
|
|
val = nvic_readl(s, offset);
|
|
} else {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"NVIC: Bad read of size %d at offset 0x%x\n",
|
|
size, offset);
|
|
val = 0;
|
|
}
|
|
}
|
|
|
|
trace_nvic_sysreg_read(addr, val, size);
|
|
return val;
|
|
}
|
|
|
|
static void nvic_sysreg_write(void *opaque, hwaddr addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
NVICState *s = (NVICState *)opaque;
|
|
uint32_t offset = addr;
|
|
unsigned i, startvec, end;
|
|
unsigned setval = 0;
|
|
|
|
trace_nvic_sysreg_write(addr, value, size);
|
|
|
|
switch (offset) {
|
|
case 0x100 ... 0x13f: /* NVIC Set enable */
|
|
offset += 0x80;
|
|
setval = 1;
|
|
/* fall through */
|
|
case 0x180 ... 0x1bf: /* NVIC Clear enable */
|
|
startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
|
|
|
|
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
|
|
if (value & (1 << i)) {
|
|
s->vectors[startvec + i].enabled = setval;
|
|
}
|
|
}
|
|
nvic_irq_update(s);
|
|
return;
|
|
case 0x200 ... 0x23f: /* NVIC Set pend */
|
|
/* the special logic in armv7m_nvic_set_pending()
|
|
* is not needed since IRQs are never escalated
|
|
*/
|
|
offset += 0x80;
|
|
setval = 1;
|
|
/* fall through */
|
|
case 0x280 ... 0x2bf: /* NVIC Clear pend */
|
|
startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */
|
|
|
|
for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
|
|
if (value & (1 << i)) {
|
|
s->vectors[startvec + i].pending = setval;
|
|
}
|
|
}
|
|
nvic_irq_update(s);
|
|
return;
|
|
case 0x300 ... 0x33f: /* NVIC Active */
|
|
return; /* R/O */
|
|
case 0x400 ... 0x5ef: /* NVIC Priority */
|
|
startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
|
|
|
|
for (i = 0; i < size && startvec + i < s->num_irq; i++) {
|
|
set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
|
|
}
|
|
nvic_irq_update(s);
|
|
return;
|
|
case 0xd18 ... 0xd23: /* System Handler Priority. */
|
|
for (i = 0; i < size; i++) {
|
|
unsigned hdlidx = (offset - 0xd14) + i;
|
|
set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
|
|
}
|
|
nvic_irq_update(s);
|
|
return;
|
|
}
|
|
if (size == 4) {
|
|
nvic_writel(s, offset, value);
|
|
return;
|
|
}
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
|
|
}
|
|
|
|
static const MemoryRegionOps nvic_sysreg_ops = {
|
|
.read = nvic_sysreg_read,
|
|
.write = nvic_sysreg_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static int nvic_post_load(void *opaque, int version_id)
|
|
{
|
|
NVICState *s = opaque;
|
|
unsigned i;
|
|
|
|
/* Check for out of range priority settings */
|
|
if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
|
|
s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
|
|
s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
|
|
return 1;
|
|
}
|
|
for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) {
|
|
if (s->vectors[i].prio & ~0xff) {
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
nvic_recompute_state(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_VecInfo = {
|
|
.name = "armv7m_nvic_info",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT16(prio, VecInfo),
|
|
VMSTATE_UINT8(enabled, VecInfo),
|
|
VMSTATE_UINT8(pending, VecInfo),
|
|
VMSTATE_UINT8(active, VecInfo),
|
|
VMSTATE_UINT8(level, VecInfo),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_nvic = {
|
|
.name = "armv7m_nvic",
|
|
.version_id = 4,
|
|
.minimum_version_id = 4,
|
|
.post_load = &nvic_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
|
|
vmstate_VecInfo, VecInfo),
|
|
VMSTATE_UINT32(prigroup, NVICState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property props_nvic[] = {
|
|
/* Number of external IRQ lines (so excluding the 16 internal exceptions) */
|
|
DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
static void armv7m_nvic_reset(DeviceState *dev)
|
|
{
|
|
NVICState *s = NVIC(dev);
|
|
|
|
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
|
|
s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
|
|
/* MEM, BUS, and USAGE are enabled through
|
|
* the System Handler Control register
|
|
*/
|
|
s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
|
|
s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
|
|
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
|
|
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
|
|
|
|
s->vectors[ARMV7M_EXCP_RESET].prio = -3;
|
|
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
|
|
s->vectors[ARMV7M_EXCP_HARD].prio = -1;
|
|
|
|
/* Strictly speaking the reset handler should be enabled.
|
|
* However, we don't simulate soft resets through the NVIC,
|
|
* and the reset vector should never be pended.
|
|
* So we leave it disabled to catch logic errors.
|
|
*/
|
|
|
|
s->exception_prio = NVIC_NOEXC_PRIO;
|
|
s->vectpending = 0;
|
|
}
|
|
|
|
static void nvic_systick_trigger(void *opaque, int n, int level)
|
|
{
|
|
NVICState *s = opaque;
|
|
|
|
if (level) {
|
|
/* SysTick just asked us to pend its exception.
|
|
* (This is different from an external interrupt line's
|
|
* behaviour.)
|
|
*/
|
|
armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
|
|
}
|
|
}
|
|
|
|
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
NVICState *s = NVIC(dev);
|
|
SysBusDevice *systick_sbd;
|
|
Error *err = NULL;
|
|
|
|
s->cpu = ARM_CPU(qemu_get_cpu(0));
|
|
assert(s->cpu);
|
|
|
|
if (s->num_irq > NVIC_MAX_IRQ) {
|
|
error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq);
|
|
return;
|
|
}
|
|
|
|
qdev_init_gpio_in(dev, set_irq_level, s->num_irq);
|
|
|
|
/* include space for internal exception vectors */
|
|
s->num_irq += NVIC_FIRST_IRQ;
|
|
|
|
object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
|
|
if (err != NULL) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
systick_sbd = SYS_BUS_DEVICE(&s->systick);
|
|
sysbus_connect_irq(systick_sbd, 0,
|
|
qdev_get_gpio_in_named(dev, "systick-trigger", 0));
|
|
|
|
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
|
|
* and looks like this:
|
|
* 0x004 - ICTR
|
|
* 0x010 - 0xff - systick
|
|
* 0x100..0x7ec - NVIC
|
|
* 0x7f0..0xcff - Reserved
|
|
* 0xd00..0xd3c - SCS registers
|
|
* 0xd40..0xeff - Reserved or Not implemented
|
|
* 0xf00 - STIR
|
|
*
|
|
* At the moment there is only one thing in the container region,
|
|
* but we leave it in place to allow us to pull systick out into
|
|
* its own device object later.
|
|
*/
|
|
memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
|
|
/* The system register region goes at the bottom of the priority
|
|
* stack as it covers the whole page.
|
|
*/
|
|
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
|
|
"nvic_sysregs", 0x1000);
|
|
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
|
|
memory_region_add_subregion_overlap(&s->container, 0x10,
|
|
sysbus_mmio_get_region(systick_sbd, 0),
|
|
1);
|
|
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
|
|
}
|
|
|
|
static void armv7m_nvic_instance_init(Object *obj)
|
|
{
|
|
/* We have a different default value for the num-irq property
|
|
* than our superclass. This function runs after qdev init
|
|
* has set the defaults from the Property array and before
|
|
* any user-specified property setting, so just modify the
|
|
* value in the GICState struct.
|
|
*/
|
|
DeviceState *dev = DEVICE(obj);
|
|
NVICState *nvic = NVIC(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
|
|
qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
|
|
|
|
sysbus_init_irq(sbd, &nvic->excpout);
|
|
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
|
|
qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
|
|
}
|
|
|
|
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_nvic;
|
|
dc->props = props_nvic;
|
|
dc->reset = armv7m_nvic_reset;
|
|
dc->realize = armv7m_nvic_realize;
|
|
}
|
|
|
|
static const TypeInfo armv7m_nvic_info = {
|
|
.name = TYPE_NVIC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_init = armv7m_nvic_instance_init,
|
|
.instance_size = sizeof(NVICState),
|
|
.class_init = armv7m_nvic_class_init,
|
|
.class_size = sizeof(SysBusDeviceClass),
|
|
};
|
|
|
|
static void armv7m_nvic_register_types(void)
|
|
{
|
|
type_register_static(&armv7m_nvic_info);
|
|
}
|
|
|
|
type_init(armv7m_nvic_register_types)
|