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qemu/target-ppc/translate
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Nikunj A Dadhania 125a9b2327 target-ppc: implement vexts[bh]2w and vexts[bhw]2d 
Vector Extend Sign Instructions:

vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign Halfword To Doubleword
vextsw2d: Vector Extend Sign Word To Doubleword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
 		2016-10-14 10:06:47 +11:00
..
dfp-impl.inc.c ppc: Rename #include'd .c files to .inc.c 2016-09-07 12:40:12 +10:00
dfp-ops.inc.c ppc: Rename #include'd .c files to .inc.c 2016-09-07 12:40:12 +10:00
fp-impl.inc.c target-ppc: convert st64 to use new macro 2016-09-23 10:29:40 +10:00
fp-ops.inc.c target-ppc: convert st64 to use new macro 2016-09-23 10:29:40 +10:00
spe-impl.inc.c target-ppc: convert st64 to use new macro 2016-09-23 10:29:40 +10:00
spe-ops.inc.c ppc: Rename #include'd .c files to .inc.c 2016-09-07 12:40:12 +10:00
vmx-impl.inc.c target-ppc: implement vexts[bh]2w and vexts[bhw]2d 2016-10-14 10:06:47 +11:00
vmx-ops.inc.c target-ppc: implement vexts[bh]2w and vexts[bhw]2d 2016-10-14 10:06:47 +11:00
vsx-impl.inc.c target-ppc: Implement mtvsrws instruction 2016-10-05 11:05:28 +11:00
vsx-ops.inc.c target-ppc: Implement mtvsrws instruction 2016-10-05 11:05:28 +11:00