mirror of https://gitee.com/openkylin/qemu.git
268 lines
6.8 KiB
C
268 lines
6.8 KiB
C
/*
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* libqos PCI bindings
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqos/pci.h"
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#include "hw/pci/pci_regs.h"
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#include <glib.h>
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void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
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void (*func)(QPCIDevice *dev, int devfn, void *data),
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void *data)
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{
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int slot;
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for (slot = 0; slot < 32; slot++) {
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int fn;
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for (fn = 0; fn < 8; fn++) {
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QPCIDevice *dev;
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dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
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if (!dev) {
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continue;
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}
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if (vendor_id != -1 &&
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qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
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g_free(dev);
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continue;
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}
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if (device_id != -1 &&
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qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
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g_free(dev);
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continue;
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}
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func(dev, QPCI_DEVFN(slot, fn), data);
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}
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}
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}
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QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
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{
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QPCIDevice *dev;
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dev = g_malloc0(sizeof(*dev));
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dev->bus = bus;
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dev->devfn = devfn;
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if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
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g_free(dev);
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return NULL;
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}
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return dev;
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}
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void qpci_device_enable(QPCIDevice *dev)
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{
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uint16_t cmd;
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/* FIXME -- does this need to be a bus callout? */
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cmd = qpci_config_readw(dev, PCI_COMMAND);
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cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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qpci_config_writew(dev, PCI_COMMAND, cmd);
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/* Verify the bits are now set. */
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cmd = qpci_config_readw(dev, PCI_COMMAND);
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g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
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g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
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g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
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}
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uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id)
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{
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uint8_t cap;
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uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
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do {
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cap = qpci_config_readb(dev, addr);
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if (cap != id) {
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addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
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}
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} while (cap != id && addr != 0);
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return addr;
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}
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void qpci_msix_enable(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t val;
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uint32_t table;
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uint8_t bir_table;
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uint8_t bir_pba;
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void *offset;
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
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table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
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bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
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offset = qpci_iomap(dev, bir_table, NULL);
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dev->msix_table = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
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table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
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bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
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if (bir_pba != bir_table) {
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offset = qpci_iomap(dev, bir_pba, NULL);
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}
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dev->msix_pba = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
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g_assert(dev->msix_table != NULL);
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g_assert(dev->msix_pba != NULL);
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dev->msix_enabled = true;
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}
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void qpci_msix_disable(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t val;
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g_assert(dev->msix_enabled);
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
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val & ~PCI_MSIX_FLAGS_ENABLE);
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qpci_iounmap(dev, dev->msix_table);
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qpci_iounmap(dev, dev->msix_pba);
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dev->msix_enabled = 0;
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dev->msix_table = NULL;
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dev->msix_pba = NULL;
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}
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bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
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{
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uint32_t pba_entry;
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uint8_t bit_n = entry % 32;
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void *addr = dev->msix_pba + (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
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g_assert(dev->msix_enabled);
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pba_entry = qpci_io_readl(dev, addr);
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qpci_io_writel(dev, addr, pba_entry & ~(1 << bit_n));
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return (pba_entry & (1 << bit_n)) != 0;
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}
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bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
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{
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uint8_t addr;
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uint16_t val;
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void *vector_addr = dev->msix_table + (entry * PCI_MSIX_ENTRY_SIZE);
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g_assert(dev->msix_enabled);
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
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g_assert_cmphex(addr, !=, 0);
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val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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if (val & PCI_MSIX_FLAGS_MASKALL) {
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return true;
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} else {
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return (qpci_io_readl(dev, vector_addr + PCI_MSIX_ENTRY_VECTOR_CTRL)
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& PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
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}
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}
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uint16_t qpci_msix_table_size(QPCIDevice *dev)
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{
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uint8_t addr;
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uint16_t control;
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addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
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g_assert_cmphex(addr, !=, 0);
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control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
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return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
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}
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uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readb(dev->bus, dev->devfn, offset);
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}
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uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readw(dev->bus, dev->devfn, offset);
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}
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uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readl(dev->bus, dev->devfn, offset);
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}
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void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
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{
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dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
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{
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dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
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{
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dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
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}
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uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readb(dev->bus, data);
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}
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uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readw(dev->bus, data);
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}
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uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readl(dev->bus, data);
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}
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void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
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{
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dev->bus->io_writeb(dev->bus, data, value);
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}
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void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
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{
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dev->bus->io_writew(dev->bus, data, value);
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}
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void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
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{
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dev->bus->io_writel(dev->bus, data, value);
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}
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void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
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{
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return dev->bus->iomap(dev->bus, dev, barno, sizeptr);
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}
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void qpci_iounmap(QPCIDevice *dev, void *data)
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{
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dev->bus->iounmap(dev->bus, data);
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}
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