qemu/target
Peter Maydell 55bb1a55c7 arm: Remove unnecessary includes of hw/arm/arm.h
The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
2019-05-23 14:47:43 +01:00
..
alpha target/alpha: Fix user-only floating-point exceptions 2019-05-19 07:30:03 -07:00
arm arm: Remove unnecessary includes of hw/arm/arm.h 2019-05-23 14:47:43 +01:00
cris Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
hppa tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
i386 Introduce qemu_guest_getrandom. 2019-05-23 12:57:17 +01:00
lm32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
m68k code cleanup, switch to transaction_failed hook 2019-05-17 10:28:23 +01:00
microblaze tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
mips tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
moxie tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
nios2 Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
openrisc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
ppc target/ppc: Use qemu_guest_getrandom for DARN 2019-05-22 12:38:54 -04:00
riscv Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
s390x s390x update: 2019-05-21 16:30:13 +01:00
sh4 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
sparc Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
tilegx target/tilegx: Convert to CPUClass::tlb_fill 2019-05-10 11:12:50 -07:00
tricore Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
unicore32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
xtensa target/xtensa: SR reorganization and options for modern cores 2019-05-21 10:44:21 +01:00