qemu/target/xtensa
Max Filippov 9e03ade441 target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
..
core-dc232b
core-dc233c
core-fsf
Makefile.objs
core-dc232b.c
core-dc233c.c
core-fsf.c
cpu-qom.h
cpu.c target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
cpu.h target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
gdbstub.c
helper.c target/xtensa: implement RUNSTALL 2017-01-15 13:01:55 -08:00
helper.h target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
import_core.sh
monitor.c
op_helper.c target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
overlay_tool.h target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
translate.c target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00
xtensa-semi.c