Paul Brook d4c430a80f Large page TLB flush ... QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>		2010-03-17 02:44:41 +00:00
..
TODO	target-mips: add copyright notice for mips16 work	2009-12-13 20:20:20 +01:00
cpu.h	Target specific usermode cleanup	2010-03-12 18:44:24 +00:00
exec.h	kill regs_to_env and env_to_regs	2010-01-19 16:31:02 -06:00
helper.c	Large page TLB flush	2010-03-17 02:44:41 +00:00
helper.h	target-mips: use physical address in lladdr	2009-11-30 16:18:28 +01:00
machine.c	target-mips: rename CP0_LLAddr into lladdr	2009-11-22 14:12:13 +01:00
mips-defs.h	target-mips: update address space definitions	2010-03-13 11:35:55 +01:00
op_helper.c	target-mips: don't call cpu_loop_exit() from helper.c	2010-02-06 17:23:33 +01:00
translate.c	target-mips: use newer logical ops	2010-03-04 17:42:03 +01:00
translate_init.c	target-mips: No MIPS16 support for 4Kc, 4KEc cores	2009-12-17 00:28:58 +01:00