mirror of https://gitee.com/openkylin/qemu.git
1015 lines
36 KiB
Plaintext
1015 lines
36 KiB
Plaintext
Rocker Network Switch Register Programming Guide
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Copyright (c) Scott Feldman <sfeldma@gmail.com>
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Copyright (c) Neil Horman <nhorman@tuxdriver.com>
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Version 0.11, 12/29/2014
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LICENSE
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=======
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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SECTION 1: Introduction
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=======================
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Overview
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--------
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This document describes the hardware/software interface for the Rocker switch
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device. The intended audience is authors of OS drivers and device emulation
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software.
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Notations and Conventions
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-------------------------
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o In register descriptions, [n:m] indicates a range from bit n to bit m,
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inclusive.
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o Use of leading 0x indicates a hexadecimal number.
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o Use of leading 0b indicates a binary number.
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o The use of RSVD or Reserved indicates that a bit or field is reserved for
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future use.
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o Field width is in bytes, unless otherwise noted.
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o Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
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on read
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o TLV values in network-byte-order are designated with (N).
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SECTION 2: PCI Configuration Registers
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======================================
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PCI Configuration Space
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-----------------------
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Each switch instance registers as a PCI device with PCI configuration space:
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offset width description value
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---------------------------------------------
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0x0 2 Vendor ID 0x1b36
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0x2 2 Device ID 0x0006
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0x4 4 Command/Status
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0x8 1 Revision ID 0x01
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0x9 3 Class code 0x2800
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0xC 1 Cache line size
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0xD 1 Latency timer
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0xE 1 Header type
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0xF 1 Built-in self test
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0x10 4 Base address low
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0x14 4 Base address high
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0x18-28 Reserved
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0x2C 2 Subsystem vendor ID *
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0x2E 2 Subsystem ID *
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0x30-38 Reserved
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0x3C 1 Interrupt line
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0x3D 1 Interrupt pin 0x00
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0x3E 1 Min grant 0x00
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0x3D 1 Max latency 0x00
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0x40 1 TRDY timeout
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0x41 1 Retry count
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0x42 2 Reserved
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* Assigned by sub-system implementation
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SECTION 3: Memory-Mapped Register Space
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=======================================
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There are two memory-mapped BARs. BAR0 maps device register space and is
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0x2000 in size. BAR1 maps MSI-X vector and PBA tables and is also 0x2000 in
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size, allowing for 256 MSI-X vectors.
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All registers are 4 or 8 bytes long. It is assumed host software will access 4
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byte registers with one 4-byte access, and 8 byte registers with either two
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4-byte accesses or a single 8-byte access. In the case of two 4-byte accesses,
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access must be lower and then upper 4-bytes, in that order.
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BAR0 device register space is organized as follows:
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offset description
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------------------------------------------------------
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0x0000-0x000f Bogus registers to catch misbehaving
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drivers. Writes do nothing. Reads
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back as 0xDEADBABE.
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0x0010-0x00ff Test registers
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0x0300-0x03ff General purpose registers
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0x1000-0x1fff Descriptor control
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Holes in register space are reserved. Writes to reserved registers do nothing.
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Reads to reserved registers read back as 0.
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No fancy stuff like write-combining is enabled on any of the registers.
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BAR1 MSI-X register space is organized as follows:
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offset description
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------------------------------------------------------
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0x0000-0x0fff MSI-X vector table (256 vectors total)
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0x1000-0x1fff MSI-X PBA table
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SECTION 4: Interrupts, DMA, and Endianness
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==========================================
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PCI Interrupts
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--------------
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The device supports only MSI-X interrupts. BAR1 memory-mapped region contains
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the MSI-X vector and PBA tables, with support for up to 256 MSI-X vectors.
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The vector assignment is:
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vector description
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-----------------------------------------------------
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0 Command descriptor ring completion
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1 Event descriptor ring completion
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2 Test operation completion
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3 RSVD
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4-255 Tx and Rx descriptor ring completion
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Tx vector is even
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Rx vector is odd
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A MSI-X vector table entry is 16 bytes:
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field offset width description
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-------------------------------------------------------------
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lower_addr 0x0 4 [31:2] message address[31:2]
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[1:0] Rsvd (4 byte alignment
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required)
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upper_addr 0x4 4 [31:19] Rsvd
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[14:0] message address[46:32]
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data 0x8 4 message data[31:0]
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control 0xc 4 [31:1] Rsvd
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[0] mask (0 = enable,
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1 = masked)
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Software should install the Interrupt Service Routine (ISR) before any ports
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are enabled or any commands are issued on the command ring.
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DMA Operations
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--------------
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DMA operations are used for packet DMA to/from the CPU, command and event
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processing. Command processing includes statistical counters and table dumps,
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table insertion/deletion, and more. Event processing provides an async
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notification method for device-originating events. Each DMA operation has a
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set of control registers to manage a descriptor ring. The descriptor rings are
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allocated from contiguous host DMA-able memory and registers specify the rings
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base address, size and current head and tail indices. Software always writes
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the head, and hardware always writes the tail.
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The higher-order bit of DMA_DESC_COMP_ERR is used to mark hardware completion
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of a descriptor. Software will clear this bit when posting a descriptor to the
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ring, and hardware will set this bit when the descriptor is complete.
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Descriptor ring sizes must be a power of 2 and range from 2 to 64K entries.
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Descriptor rings' base address must be 8-byte aligned. Descriptors must be
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packed within ring. Each descriptor in each ring must also be aligned on an 8
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byte boundary. Each descriptor ring will have these registers:
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DMA_DESC_xxx_BASE_ADDR, offset 0x1000 + (x * 32), 64-bit, (R/W)
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DMA_DESC_xxx_SIZE, offset 0x1008 + (x * 32), 32-bit, (R/W)
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DMA_DESC_xxx_HEAD, offset 0x100c + (x * 32), 32-bit, (R/W)
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DMA_DESC_xxx_TAIL, offset 0x1010 + (x * 32), 32-bit, (R)
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DMA_DESC_xxx_CTRL, offset 0x1014 + (x * 32), 32-bit, (W)
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DMA_DESC_xxx_CREDITS, offset 0x1018 + (x * 32), 32-bit, (R/W)
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DMA_DESC_xxx_RSVD1, offset 0x101c + (x * 32), 32-bit, (R/W)
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Where x is descriptor ring index:
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index ring
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--------------------
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0 CMD
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1 EVENT
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2 TX (port 0)
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3 RX (port 0)
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4 TX (port 1)
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5 RX (port 1)
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.
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.
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.
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124 TX (port 61)
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125 RX (port 61)
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126 Resv
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127 Resv
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Writing BASE_ADDR or SIZE will reset HEAD and TAIL to zero. HEAD cannot be
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written past TAIL. To do so would wrap the ring. An empty ring is when HEAD
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== TAIL. A full ring is when HEAD is one position behind TAIL. Both HEAD and
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TAIL increment and modulo wrap at the ring size.
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CTRL register bits:
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bit name description
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------------------------------------------------------------------------
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[0] CTRL_RESET Reset the descriptor ring
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[1:31] Reserved
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All descriptor types share some common fields:
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field width description
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-------------------------------------------------------------------
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DMA_DESC_BUF_ADDR 8 Phys addr of desc payload, 8-byte
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aligned
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DMA_DESC_COOKIE 8 Desc cookie for completion matching,
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upper-most bit is reserved
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DMA_DESC_BUF_SIZE 2 Desc payload size in bytes
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DMA_DESC_TLV_SIZE 2 Desc payload total size in bytes
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used for TLVs. Must be <=
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DMA_DESC_BUF_SIZE.
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DMA_DESC_COMP_ERR 2 Completion status of associated
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desc payload. High order bit is
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clear on new descs, toggled by
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hw for completed items.
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To support forward- and backward-compatibility, descriptor and completion
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payloads are specified in TLV format. Fields are packed with Type=field name,
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Length=field length, and Value=field value. Software will ignore unknown fields
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filled in by the switch. Likewise, the switch will ignore unknown fields
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filled in by software.
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Descriptor payload buffer is 8-byte aligned and TLVs are 8-byte aligned. The
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value within a TLV is also 8-byte aligned. The (packed, 8 byte) TLV header is:
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field width description
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-----------------------------
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type 4 TLV type
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len 2 TLV value length
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pad 2 Reserved
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The alignment requirements for descriptors and TLVs are to avoid unaligned
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access exceptions in software. Note that the payload for each TLV is also
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8 byte aligned.
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Figure 1 shows an example descriptor buffer with two TLVs.
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<------- 8 bytes ------->
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8-byte +––––+ +–––––––––––+–––––+–––––+ +–+
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align | type | len | pad | TLV#1 hdr |
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+–––––––––––+–––––+–––––+ (len=22) |
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| | |
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| value | TVL#1 value |
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| | (padded to 8-byte |
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| +–––––+ alignment) |
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| |/////| |
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8-byte +––––+ +–––––––––––+–––––––––––+ |
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align | type | len | pad | TLV#2 hdr DESC_BUF_SIZE
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+–––––+–––––+–––––+–––––+ (len=2) |
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|value|/////////////////| TLV#2 value |
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+–––––+/////////////////| |
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|///////////////////////| |
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|///////////////////////| |
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|///////////////////////| |
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|////////unused/////////| |
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|////////space//////////| |
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|///////////////////////| |
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|///////////////////////| |
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|///////////////////////| |
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+–––––––––––––––––––––––+ +–+
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fig. 1
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TLVs can be nested within the NEST TLV type.
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Interrupt credits
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^^^^^^^^^^^^^^^^^
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MSI-X vectors used for descriptor ring completions use a credit mechanism for
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efficient device, PCIe bus, OS and driver operations. Each descriptor ring has
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a credit count which represents the number of outstanding descriptors to be
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processed by the driver. As the device marks descriptors complete, the credit
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count is incremented. As the driver processes those outstanding descriptors,
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it returns credits back to the device. This way, the device knows the driver's
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progress and can make decisions about when to fire the next interrupt or not.
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When the credit count is zero, and the first descriptors are posted for the
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driver, a single interrupt is fired. Once the interrupt is fired, the
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interrupt is disabled (auto-masked*). In response to the interrupt, the driver
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will process descriptors and PIO write a returned credit value for that
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descriptor ring. If the driver returns all credits (the driver caught up with
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the device and there is no outstanding work), then the interrupt is unmasked,
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but not fired. If only partial credits are returned, the interrupt remains
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masked but the device generates an interrupt, signaling the driver that more
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outstanding work is available.
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(* this masking is unrelated to the MSI-X interrupt mask register)
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Endianness
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----------
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Device registers are hard-coded to little-endian (LE). The driver should
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convert to/from host endianness to LE for device register accesses.
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Descriptors are LE. Descriptor buffer TLVs will have LE type and length
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fields, but the value field can either be LE or network-byte-order, depending
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on context. TLV values containing network packet data will be in network-byte
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order. A TLV value containing a field or mask used to compare against network
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packet data is network-byte order. For example, flow match fields (and masks)
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are network-byte-order since they're matched directly, byte-by-byte, against
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network packet data. All non-network-packet TLV multi-byte values will be LE.
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TLV values in network-byte-order are designated with (N).
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SECTION 5: Test Registers
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=========================
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Rocker has several test registers to support troubleshooting register access,
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interrupt generation, and DMA operations:
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TEST_REG, offset 0x0010, 32-bit (R/W)
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TEST_REG64, offset 0x0018, 64-bit (R/W)
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TEST_IRQ, offset 0x0020, 32-bit (R/W)
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TEST_DMA_ADDR, offset 0x0028, 64-bit (R/W)
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TEST_DMA_SIZE, offset 0x0030, 32-bit (R/W)
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TEST_DMA_CTRL, offset 0x0034, 32-bit (R/W)
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Reads to TEST_REG and TEST_REG64 will read a value equal to twice the last
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value written to the register. The 32-bit and 64-bit versions are for testing
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32-bit and 64-bit host accesses.
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A vector can be written to TEST_IRQ and the device will generate an interrupt
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for that vector.
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To test basic DMA operations, allocate a DMA-able host buffer and put the
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buffer address into TEST_DMA_ADDR and size into TEST_DMA_SIZE. Then, write to
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TEST_DMA_CTRL to manipulate the buffer contents. TEST_DMA_CTRL operations are:
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operation value description
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-----------------------------------------------------------
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TEST_DMA_CTRL_CLEAR 1 clear buffer
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TEST_DMA_CTRL_FILL 2 fill buffer bytes with 0x96
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TEST_DMA_CTRL_INVERT 4 invert bytes in buffer
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Various buffer address and sizes should be tested to verify no address boundary
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issue exists. In particular, buffers that start on odd-8-byte boundary and/or
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span multiple PAGE sizes should be tested.
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SECTION 6: Ports
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================
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Physical and Logical Ports
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------------------------------------
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The switch supports up to 62 physical (front-panel) ports. Register
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PORT_PHYS_COUNT returns the actual number of physical ports available:
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PORT_PHYS_COUNT, offset 0x0304, 32-bit, (R)
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In addition to front-panel ports, the switch supports logical ports for
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tunnels.
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Front-panel ports and logical tunnel ports are mapped into a single 32-bit port
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space. A special CPU port is assigned port 0. The front-panel ports are
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mapped to ports 1-62. A special loopback port is assigned port 63. Logical
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tunnel ports are assigned ports 0x0001000-0x0001ffff.
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To summarize the port assignments:
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port mapping
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-------------------------------------------------------
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0 CPU port (for packets to/from host CPU)
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1-62 front-panel physical ports
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63 loopback port
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64-0x0000ffff RSVD
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0x00010000-0x0001ffff logical tunnel ports
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0x00020000-0xffffffff RSVD
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Physical Port Mode
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------------------
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Switch front-panel ports operate in a mode. Currently, the only mode is
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OF-DPA. OF-DPA[1] mode is based on OpenFlow Data Plane Abstraction (OF-DPA)
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Abstract Switch Specification, Version 1.0, from Broadcom Corporation. To
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set/get the mode for front-panel ports, see port settings, below.
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Port Settings
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-------------
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Link status for all front-panel ports is available via PORT_PHYS_LINK_STATUS:
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PORT_PHYS_LINK_STATUS, offset 0x0310, 64-bit, (R)
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Value is port bitmap. Bits 0 and 63 always read 0. Bits 1-62
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read 1 for link UP and 0 for link DOWN for respective front-panel ports.
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Other properties for front-panel ports are available via DMA CMD descriptors:
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Get PORT_SETTINGS descriptor:
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field width description
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----------------------------------------------
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PORT_SETTINGS 2 CMD_GET
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PPORT 4 Physical port #
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Get PORT_SETTINGS completion:
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field width description
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----------------------------------------------
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PPORT 4 Physical port #
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SPEED 4 Current port interface speed, in Mbps
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DUPLEX 1 1 = Full, 0 = Half
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AUTONEG 1 1 = enabled, 0 = disabled
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MACADDR 6 Port MAC address
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MODE 1 0 = OF-DPA
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LEARNING 1 MAC address learning on port
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1 = enabled
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0 = disabled
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PHYS_NAME <var> Physical port name (string)
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Set PORT_SETTINGS descriptor:
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field width description
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----------------------------------------------
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PORT_SETTINGS 2 CMD_SET
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PPORT 4 Physical port #
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SPEED 4 Port interface speed, in Mbps
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DUPLEX 1 1 = Full, 0 = Half
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AUTONEG 1 1 = enabled, 0 = disabled
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MACADDR 6 Port MAC address
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MODE 1 0 = OF-DPA
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Port Enable
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-----------
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Front-panel ports are initially disabled, which means port ingress and egress
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packets will be dropped. To enable or disable a port, use PORT_PHYS_ENABLE:
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PORT_PHYS_ENABLE: offset 0x0318, 64-bit, (R/W)
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Value is bitmap of first 64 ports. Bits 0 and 63 are ignored
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and always read as 0. Write 1 to enable port; write 0 to disable it.
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Default is 0.
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SECTION 7: Switch Control
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=========================
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This section covers switch-wide register settings.
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Control
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-------
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This register is used for low level control of the switch.
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CONTROL: offset 0x0300, 32-bit, (W)
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bit name description
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------------------------------------------------------------------------
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[0] CONTROL_RESET If set, device will perform reset
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[1:31] Reserved
|
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|
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Switch ID
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---------
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The switch has a SWITCH_ID to be used by software to uniquely identify the
|
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switch:
|
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SWITCH_ID: offset 0x0320, 64-bit, (R)
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Value is opaque to switch software and no special encoding is implied.
|
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SECTION 8: Events
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=================
|
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Non-I/O asynchronous events from the device are notified to the host using the
|
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event ring. The TLV structure for events is:
|
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field width description
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---------------------------------------------------
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TYPE 4 Event type, one of:
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1: LINK_CHANGED
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2: MAC_VLAN_SEEN
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INFO <nest> Event info (details below)
|
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|
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Link Changed Event
|
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------------------
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When link status changes on a physical port, this event is generated.
|
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field width description
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---------------------------------------------------
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INFO <nest>
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PPORT 4 Physical port
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LINKUP 1 Link status:
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0: down
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1: up
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MAC VLAN Seen Event
|
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-------------------
|
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|
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When a packet ingresses on a port and the source MAC/VLAN isn't known to the
|
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device, the device will generate this event. In response to the event, the
|
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driver should install to the device the MAC/VLAN on the port into the bridge
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table. Once installed, the MAC/VLAN is known on the port and this event will
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no longer be generated.
|
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field width description
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---------------------------------------------------
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INFO <nest>
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PPORT 4 Physical port
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MAC 6 MAC address
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VLAN 2 VLAN ID
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SECTION 9: CPU Packet Processing
|
||
================================
|
||
|
||
Ingress packets directed to the host CPU for further processing are delivered
|
||
in the DMA RX ring. Likewise, host CPU originating packets destined to egress
|
||
on switch ports are scheduled by software using the DMA TX ring.
|
||
|
||
Tx Packet Processing
|
||
--------------------
|
||
|
||
Software schedules packets for egress on switch ports using the DMA TX ring. A
|
||
TX descriptor buffer describes the packet location and size in host DMA-able
|
||
memory, the destination port, and any hardware-offload functions (such as L3
|
||
payload checksum offload). Software then bumps the descriptor head to signal
|
||
hardware of new Tx work. In response, hardware will DMA read Tx descriptors up
|
||
to head, DMA read descriptor buffer and packet data, perform offloading
|
||
functions, and finally frame packet on wire (network). Once packet processing
|
||
is complete, hardware will writeback status to descriptor(s) to signal to
|
||
software that Tx is complete and software resources (e.g. skb) backing packet
|
||
can be released.
|
||
|
||
Figure 2 shows an example 3-fragment packet queued with one Tx descriptor. A
|
||
TLV is used for each packet fragment.
|
||
|
||
pkt frag 1
|
||
+–––––––+ +–+
|
||
+–––+ | |
|
||
desc buf | | | |
|
||
+––––––––+ | | | |
|
||
Tx ring +–––+ +–––––+ | | |
|
||
+–––––––––+ | | TLVs | +–––––––+ |
|
||
| +–––+ +––––––––+ pkt frag 2 |
|
||
| desc 0 | | +–––––+ +–––––––+ |
|
||
+–––––––––+ | TLVs | +–––+ | |
|
||
head+–+ | +––––––––+ | | |
|
||
| desc 1 | | +–––––+ +–––––––+ |pkt
|
||
+–––––––––+ | TLVs | | |
|
||
| | +––––––––+ | pkt frag 3 |
|
||
| | | +–––––––+ |
|
||
+–––––––––+ +–––+ | |
|
||
| | | | |
|
||
| | | | |
|
||
+–––––––––+ | | |
|
||
| | | | |
|
||
| | | | |
|
||
+–––––––––+ | | |
|
||
| | +–––––––+ +–+
|
||
| |
|
||
+–––––––––+
|
||
|
||
fig 2.
|
||
|
||
The TLVs for Tx descriptor buffer are:
|
||
|
||
field width description
|
||
---------------------------------------------------------------------
|
||
PPORT 4 Destination physical port #
|
||
TX_OFFLOAD 1 Hardware offload modes:
|
||
0: no offload
|
||
1: insert IP csum (ipv4 only)
|
||
2: insert TCP/UDP csum
|
||
3: L3 csum calc and insert
|
||
into csum offset (TX_L3_CSUM_OFF)
|
||
16-bit 1's complement csum value.
|
||
IPv4 pseudo-header and IP
|
||
already calculated by OS
|
||
and inserted.
|
||
4: TSO (TCP Segmentation Offload)
|
||
TX_L3_CSUM_OFF 2 For L3 csum offload mode, the offset,
|
||
from the beginning of the packet,
|
||
of the csum field in the L3 header
|
||
TX_TSO_MSS 2 For TSO offload mode, the
|
||
Maximum Segment Size in bytes
|
||
TX_TSO_HDR_LEN 2 For TSO offload mode, the
|
||
length of ethernet, IP, and
|
||
TCP/UDP headers, including IP
|
||
and TCP options.
|
||
TX_FRAGS <array> Packet fragments
|
||
TX_FRAG <nest> Packet fragment
|
||
TX_FRAG_ADDR 8 DMA address of packet fragment
|
||
TX_FRAG_LEN 2 Packet fragment length
|
||
|
||
Possible status return codes in descriptor on completion are:
|
||
|
||
DESC_COMP_ERR reason
|
||
--------------------------------------------------------------------
|
||
0 OK
|
||
-ROCKER_ENXIO address or data read err on desc buf or packet
|
||
fragment
|
||
-ROCKER_EINVAL bad pport or TSO or csum offloading error
|
||
-ROCKER_ENOMEM no memory for internal staging tx fragment
|
||
|
||
Rx Packet Processing
|
||
--------------------
|
||
|
||
For packets ingressing on switch ports that are not forwarded by the switch but
|
||
rather directed to the host CPU for further processing are delivered in the DMA
|
||
RX ring. Rx descriptor buffers are allocated by software and placed on the
|
||
ring. Hardware will fill Rx descriptor buffers with packet data, write the
|
||
completion, and signal to software that a new packet is ready. Since Rx packet
|
||
size is not known a-priori, the Rx descriptor buffer must be allocated for
|
||
worst-case packet size. A single Rx descriptor will contain the entire Rx
|
||
packet data in one RX_FRAG. Other Rx TLVs describe and hardware offloads
|
||
performed on the packet, such as checksum validation.
|
||
|
||
The TLVs for Rx descriptor buffer are:
|
||
|
||
field width description
|
||
---------------------------------------------------
|
||
PPORT 4 Source physical port #
|
||
RX_FLAGS 2 Packet parsing flags:
|
||
(1 << 0): IPv4 packet
|
||
(1 << 1): IPv6 packet
|
||
(1 << 2): csum calculated
|
||
(1 << 3): IPv4 csum good
|
||
(1 << 4): IP fragment
|
||
(1 << 5): TCP packet
|
||
(1 << 6): UDP packet
|
||
(1 << 7): TCP/UDP csum good
|
||
(1 << 8): Offload forward
|
||
RX_CSUM 2 IP calculated checksum:
|
||
IPv4: IP payload csum
|
||
IPv6: header and payload csum
|
||
(Only valid is RX_FLAGS:csum calc is set)
|
||
RX_FRAG_ADDR 8 DMA address of packet fragment
|
||
RX_FRAG_MAX_LEN 2 Packet maximum fragment length
|
||
RX_FRAG_LEN 2 Actual packet fragment length after receive
|
||
|
||
Offload forward RX_FLAG indicates the device has already forwarded the packet
|
||
so the host CPU should not also forward the packet.
|
||
|
||
Possible status return codes in descriptor on completion are:
|
||
|
||
DESC_COMP_ERR reason
|
||
--------------------------------------------------------------------
|
||
0 OK
|
||
-ROCKER_ENXIO address or data read err on desc buf
|
||
-ROCKER_ENOMEM no memory for internal staging desc buf
|
||
-ROCKER_EMSGSIZE Rx descriptor buffer wasn't big enough to contain
|
||
packet data TLV and other TLVs.
|
||
|
||
|
||
SECTION 10: OF-DPA Mode
|
||
======================
|
||
|
||
OF-DPA mode allows the switch to offload flow packet processing functions to
|
||
hardware. An OpenFlow controller would communicate with an OpenFlow agent
|
||
installed on the switch. The OpenFlow agent would (directly or indirectly)
|
||
communicate with the Rocker switch driver, which in turn would program switch
|
||
hardware with flow functionality, as defined in OF-DPA. The block diagram is:
|
||
|
||
+–––––––––––––––----–––+
|
||
| OF |
|
||
| Remote Controller |
|
||
+––––––––+––----–––––––+
|
||
|
|
||
|
|
||
+––––––––+–––––––––+
|
||
| OF |
|
||
| Local Agent |
|
||
+––––––––––––––––––+
|
||
| |
|
||
| Rocker Driver |
|
||
+––––––––––––––––––+
|
||
<this spec>
|
||
+––––––––––––––––––+
|
||
| |
|
||
| Rocker Switch |
|
||
+––––––––––––––––––+
|
||
|
||
To participate in flow functions, ports must be configure for OF-DPA mode
|
||
during switch initialization.
|
||
|
||
OF-DPA Flow Table Interface
|
||
---------------------------
|
||
|
||
There are commands to add, modify, delete, and get stats of flow table entries.
|
||
The commands are issued using the DMA CMD descriptor ring. The following
|
||
commands are defined:
|
||
|
||
CMD_ADD: add an entry to flow table
|
||
CMD_MOD: modify an entry in flow table
|
||
CMD_DEL: delete an entry from flow table
|
||
CMD_GET_STATS: get stats for flow entry
|
||
|
||
TLVs for add and modify commands are:
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_CMD 2 CMD_[ADD|MOD]
|
||
OF_DPA_TBL 2 Flow table ID
|
||
0: ingress port
|
||
10: vlan
|
||
20: termination mac
|
||
30: unicast routing
|
||
40: multicast routing
|
||
50: bridging
|
||
60: ACL policy
|
||
OF_DPA_PRIORITY 4 Flow priority
|
||
OF_DPA_HARDTIME 4 Hard timeout for flow
|
||
OF_DPA_IDLETIME 4 Idle timeout for flow
|
||
OF_DPA_COOKIE 8 Cookie
|
||
|
||
Additional TLVs based on flow table ID:
|
||
|
||
Table ID 0: ingress port
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_IN_PPORT 4 ingress physical port number
|
||
OF_DPA_GOTO_TBL 2 goto table ID; zero to drop
|
||
|
||
Table ID 10: vlan
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_IN_PPORT 4 ingress physical port number
|
||
OF_DPA_VLAN_ID 2 (N) vlan ID
|
||
OF_DPA_VLAN_ID_MASK 2 (N) vlan ID mask
|
||
OF_DPA_GOTO_TBL 2 goto table ID; zero to drop
|
||
OF_DPA_NEW_VLAN_ID 2 (N) new vlan ID
|
||
|
||
Table ID 20: termination mac
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_IN_PPORT 4 ingress physical port number
|
||
OF_DPA_IN_PPORT_MASK 4 ingress physical port number mask
|
||
OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
|
||
OF_DPA_DST_MAC 6 (N) destination MAC
|
||
OF_DPA_DST_MAC_MASK 6 (N) destination MAC mask
|
||
OF_DPA_VLAN_ID 2 (N) vlan ID
|
||
OF_DPA_VLAN_ID_MASK 2 (N) vlan ID mask
|
||
OF_DPA_GOTO_TBL 2 only acceptable values are
|
||
unicast or multicast routing
|
||
table IDs
|
||
OF_DPA_OUT_PPORT 2 if specified, must be
|
||
controller, set zero otherwise
|
||
|
||
Table ID 30: unicast routing
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
|
||
OF_DPA_DST_IP 4 (N) destination IPv4 address.
|
||
Must be unicast address
|
||
OF_DPA_DST_IP_MASK 4 (N) IP mask. Must be prefix mask
|
||
OF_DPA_DST_IPV6 16 (N) destination IPv6 address.
|
||
Must be unicast address
|
||
OF_DPA_DST_IPV6_MASK 16 (N) IPv6 mask. Must be prefix mask
|
||
OF_DPA_GOTO_TBL 2 goto table ID; zero to drop
|
||
OF_DPA_GROUP_ID 4 data for GROUP action must
|
||
be an L3 Unicast group entry
|
||
|
||
Table ID 40: multicast routing
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
|
||
OF_DPA_VLAN_ID 2 (N) vlan ID
|
||
OF_DPA_SRC_IP 4 (N) source IPv4. Optional,
|
||
can contain IPv4 address,
|
||
must be completely masked
|
||
if not used
|
||
OF_DPA_SRC_IP_MASK 4 (N) IP Mask
|
||
OF_DPA_DST_IP 4 (N) destination IPv4 address.
|
||
Must be multicast address
|
||
OF_DPA_SRC_IPV6 16 (N) source IPv6 Address. Optional.
|
||
Can contain IPv6 address,
|
||
must be completely masked
|
||
if not used
|
||
OF_DPA_SRC_IPV6_MASK 16 (N) IPv6 mask.
|
||
OF_DPA_DST_IPV6 16 (N) destination IPv6 Address. Must
|
||
be multicast address
|
||
Must be multicast address
|
||
OF_DPA_GOTO_TBL 2 goto table ID; zero to drop
|
||
OF_DPA_GROUP_ID 4 data for GROUP action must
|
||
be an L3 multicast group entry
|
||
|
||
Table ID 50: bridging
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_VLAN_ID 2 (N) vlan ID
|
||
OF_DPA_TUNNEL_ID 4 tunnel ID
|
||
OF_DPA_DST_MAC 6 (N) destination MAC
|
||
OF_DPA_DST_MAC_MASK 6 (N) destination MAC mask
|
||
OF_DPA_GOTO_TBL 2 goto table ID; zero to drop
|
||
OF_DPA_GROUP_ID 4 data for GROUP action must
|
||
be a L2 Interface, L2
|
||
Multicast, L2 Flood,
|
||
or L2 Overlay group entry
|
||
as appropriate
|
||
OF_DPA_TUNNEL_LPORT 4 unicast Tenant Bridging
|
||
flows specify a tunnel
|
||
logical port ID
|
||
OF_DPA_OUT_PPORT 2 data for OUTPUT action,
|
||
restricted to CONTROLLER,
|
||
set to 0 otherwise
|
||
|
||
Table ID 60: acl policy
|
||
|
||
field width description
|
||
----------------------------------------------------
|
||
OF_DPA_IN_PPORT 4 ingress physical port number
|
||
OF_DPA_IN_PPORT_MASK 4 ingress physical port number mask
|
||
OF_DPA_ETHERTYPE 2 (N) ethertype
|
||
OF_DPA_VLAN_ID 2 (N) vlan ID
|
||
OF_DPA_VLAN_ID_MASK 2 (N) vlan ID mask
|
||
OF_DPA_VLAN_PCP 2 (N) vlan Priority Code Point
|
||
OF_DPA_VLAN_PCP_MASK 2 (N) vlan Priority Code Point mask
|
||
OF_DPA_SRC_MAC 6 (N) source MAC
|
||
OF_DPA_SRC_MAC_MASK 6 (N) source MAC mask
|
||
OF_DPA_DST_MAC 6 (N) destination MAC
|
||
OF_DPA_DST_MAC_MASK 6 (N) destination MAC mask
|
||
OF_DPA_TUNNEL_ID 4 tunnel ID
|
||
OF_DPA_SRC_IP 4 (N) source IPv4. Optional,
|
||
can contain IPv4 address,
|
||
must be completely masked
|
||
if not used
|
||
OF_DPA_SRC_IP_MASK 4 (N) IP Mask
|
||
OF_DPA_DST_IP 4 (N) destination IPv4 address.
|
||
Must be multicast address
|
||
OF_DPA_DST_IP_MASK 4 (N) IP Mask
|
||
OF_DPA_SRC_IPV6 16 (N) source IPv6 Address. Optional.
|
||
Can contain IPv6 address,
|
||
must be completely masked
|
||
if not used
|
||
OF_DPA_SRC_IPV6_MASK 16 (N) IPv6 mask
|
||
OF_DPA_DST_IPV6 16 (N) destination IPv6 Address. Must
|
||
be multicast address.
|
||
OF_DPA_DST_IPV6_MASK 16 (N) IPv6 mask
|
||
OF_DPA_SRC_ARP_IP 4 (N) source IPv4 address in the ARP
|
||
payload. Only used if ethertype
|
||
== 0x0806.
|
||
OF_DPA_SRC_ARP_IP_MASK 4 (N) IP Mask
|
||
OF_DPA_IP_PROTO 1 IP protocol
|
||
OF_DPA_IP_PROTO_MASK 1 IP protocol mask
|
||
OF_DPA_IP_DSCP 1 DSCP
|
||
OF_DPA_IP_DSCP_MASK 1 DSCP mask
|
||
OF_DPA_IP_ECN 1 ECN
|
||
OF_DPA_IP_ECN_MASK 1 ECN mask
|
||
OF_DPA_L4_SRC_PORT 2 (N) L4 source port, only for
|
||
TCP, UDP, or SCTP
|
||
OF_DPA_L4_SRC_PORT_MASK 2 (N) L4 source port mask
|
||
OF_DPA_L4_DST_PORT 2 (N) L4 source port, only for
|
||
TCP, UDP, or SCTP
|
||
OF_DPA_L4_DST_PORT_MASK 2 (N) L4 source port mask
|
||
OF_DPA_ICMP_TYPE 1 ICMP type, only if IP
|
||
protocol is 1
|
||
OF_DPA_ICMP_TYPE_MASK 1 ICMP type mask
|
||
OF_DPA_ICMP_CODE 1 ICMP code
|
||
OF_DPA_ICMP_CODE_MASK 1 ICMP code mask
|
||
OF_DPA_IPV6_LABEL 4 (N) IPv6 flow label
|
||
OF_DPA_IPV6_LABEL_MASK 4 (N) IPv6 flow label mask
|
||
OF_DPA_GROUP_ID 4 data for GROUP action
|
||
OF_DPA_QUEUE_ID_ACTION 1 write the queue ID
|
||
OF_DPA_NEW_QUEUE_ID 1 queue ID
|
||
OF_DPA_VLAN_PCP_ACTION 1 write the VLAN priority
|
||
OF_DPA_NEW_VLAN_PCP 1 VLAN priority
|
||
OF_DPA_IP_DSCP_ACTION 1 write the DSCP
|
||
OF_DPA_NEW_IP_DSCP 1 new DSCP
|
||
OF_DPA_TUNNEL_LPORT 4 restrct to valid tunnel
|
||
logical port, set to 0
|
||
otherwise.
|
||
OF_DPA_OUT_PPORT 2 data for OUTPUT action,
|
||
restricted to CONTROLLER,
|
||
set to 0 otherwise
|
||
OF_DPA_CLEAR_ACTIONS 4 if 1 packets matching flow are
|
||
dropped (all other instructions
|
||
ignored)
|
||
|
||
TLVs for flow delete and get stats command are:
|
||
|
||
field width description
|
||
---------------------------------------------------
|
||
OF_DPA_CMD 2 CMD_[DEL|GET_STATS]
|
||
OF_DPA_COOKIE 8 Cookie
|
||
|
||
On completion of get stats command, the descriptor buffer is written back with
|
||
the following TLVs:
|
||
|
||
field width description
|
||
---------------------------------------------------
|
||
OF_DPA_STAT_DURATION 4 Flow duration
|
||
OF_DPA_STAT_RX_PKTS 8 Received packets
|
||
OF_DPA_STAT_TX_PKTS 8 Transmit packets
|
||
|
||
Possible status return codes in descriptor on completion are:
|
||
|
||
DESC_COMP_ERR command reason
|
||
--------------------------------------------------------------------
|
||
0 all OK
|
||
-ROCKER_EFAULT all head or tail index outside
|
||
of ring
|
||
-ROCKER_ENXIO all address or data read err on
|
||
desc buf
|
||
-ROCKER_EMSGSIZE GET_STATS cmd descriptor buffer wasn't
|
||
big enough to contain write-back
|
||
TLVs
|
||
-ROCKER_EINVAL all invalid parameters passed in
|
||
-ROCKER_EEXIST ADD entry already exists
|
||
-ROCKER_ENOSPC ADD no space left in flow table
|
||
-ROCKER_ENOENT MOD|DEL|GET_STATS cookie invalid
|
||
|
||
Group Table Interface
|
||
---------------------
|
||
|
||
There are commands to add, modify, delete, and get stats of group table
|
||
entries. The commands are issued using the DMA CMD descriptor ring. The
|
||
following commands are defined:
|
||
|
||
CMD_ADD: add an entry to group table
|
||
CMD_MOD: modify an entry in group table
|
||
CMD_DEL: delete an entry from group table
|
||
CMD_GET_STATS: get stats for group entry
|
||
|
||
TLVs for add and modify commands are:
|
||
|
||
field width description
|
||
-----------------------------------------------------------
|
||
FLOW_GROUP_CMD 2 CMD_[ADD|MOD]
|
||
FLOW_GROUP_ID 2 Flow group ID
|
||
FLOW_GROUP_TYPE 1 Group type:
|
||
0: L2 interface
|
||
1: L2 rewrite
|
||
2: L3 unicast
|
||
3: L2 multicast
|
||
4: L2 flood
|
||
5: L3 interface
|
||
6: L3 multicast
|
||
7: L3 ECMP
|
||
8: L2 overlay
|
||
FLOW_VLAN_ID 2 Vlan ID (types 0, 3, 4, 6)
|
||
FLOW_L2_PORT 2 Port (types 0)
|
||
FLOW_INDEX 4 Index (all types but 0)
|
||
FLOW_OVERLAY_TYPE 1 Overlay sub-type (type 8):
|
||
0: Flood unicast tunnel
|
||
1: Flood multicast tunnel
|
||
2: Multicast unicast tunnel
|
||
3: Multicast multicast tunnel
|
||
FLOW_GROUP_ACTION nest
|
||
FLOW_GROUP_ID 2 next group ID in chain (all
|
||
types except 0)
|
||
FLOW_OUT_PORT 4 egress port (types 0, 8)
|
||
FLOW_POP_VLAN_TAG 1 strip outer VLAN tag (type 1
|
||
only)
|
||
FLOW_VLAN_ID 2 (types 1, 5)
|
||
FLOW_SRC_MAC 6 (types 1, 2, 5)
|
||
FLOW_DST_MAC 6 (types 1, 2)
|
||
|
||
TLVs for flow delete and get stats command are:
|
||
|
||
field width description
|
||
-----------------------------------------------------------
|
||
FLOW_GROUP_CMD 2 CMD_[DEL|GET_STATS]
|
||
FLOW_GROUP_ID 2 Flow group ID
|
||
|
||
On completion of get stats command, the descriptor buffer is written back with
|
||
the following TLVs:
|
||
|
||
field width description
|
||
---------------------------------------------------
|
||
FLOW_GROUP_ID 2 Flow group ID
|
||
FLOW_STAT_DURATION 4 Flow duration
|
||
FLOW_STAT_REF_COUNT 4 Flow reference count
|
||
FLOW_STAT_BUCKET_COUNT 4 Flow bucket count
|
||
|
||
Possible status return codes in descriptor on completion are:
|
||
|
||
DESC_COMP_ERR command reason
|
||
--------------------------------------------------------------------
|
||
0 all OK
|
||
-ROCKER_EFAULT all head or tail index outside
|
||
of ring
|
||
-ROCKER_ENXIO all address or data read err on
|
||
desc buf
|
||
-ROCKER_ENOSPC GET_STATS cmd descriptor buffer wasn't
|
||
big enough to contain write-back
|
||
TLVs
|
||
-ROCKER_EINVAL ADD|MOD invalid parameters passed in
|
||
-ROCKER_EEXIST ADD entry already exists
|
||
-ROCKER_ENOSPC ADD no space left in flow table
|
||
-ROCKER_ENOENT MOD|DEL|GET_STATS group ID invalid
|
||
-ROCKER_EBUSY DEL group reference count non-zero
|
||
-ROCKER_ENODEV ADD next group ID doesn't exist
|
||
|
||
|
||
|
||
References
|
||
==========
|
||
|
||
[1] OpenFlow Data Plane Abstraction (OF-DPA) Abstract Switch Specification,
|
||
Version 1.0, from Broadcom Corporation, February 21, 2014.
|