mirror of https://gitee.com/openkylin/qemu.git
1491 lines
44 KiB
C
1491 lines
44 KiB
C
/*
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* QEMU Sun4m & Sun4d & Sun4c System Emulator
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "qemu/error-report.h"
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#include "qemu/timer.h"
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#include "hw/sparc/sun4m.h"
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#include "hw/timer/m48t59.h"
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#include "hw/sparc/sparc32_dma.h"
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#include "hw/block/fdc.h"
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#include "sysemu/sysemu.h"
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#include "net/net.h"
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#include "hw/boards.h"
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#include "hw/scsi/esp.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/isa.h"
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#include "hw/nvram/sun_nvram.h"
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#include "hw/nvram/chrp_nvram.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/char/escc.h"
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#include "hw/empty_slot.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "sysemu/block-backend.h"
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#include "trace.h"
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#include "qemu/cutils.h"
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/*
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* Sun4m architecture was used in the following machines:
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*
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* SPARCserver 6xxMP/xx
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* SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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* SPARCclassic X (4/10)
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* SPARCstation LX/ZX (4/30)
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* SPARCstation Voyager
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* SPARCstation 10/xx, SPARCserver 10/xx
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* SPARCstation 5, SPARCserver 5
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* SPARCstation 20/xx, SPARCserver 20
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* SPARCstation 4
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*
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* See for example: http://www.sunhelp.org/faq/sunref1.html
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*/
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#define KERNEL_LOAD_ADDR 0x00004000
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#define CMDLINE_ADDR 0x007ff000
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#define INITRD_LOAD_ADDR 0x00800000
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#define PROM_SIZE_MAX (1024 * 1024)
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#define PROM_VADDR 0xffd00000
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#define PROM_FILENAME "openbios-sparc32"
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#define CFG_ADDR 0xd00000510ULL
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#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
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#define MAX_CPUS 16
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#define MAX_PILS 16
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#define MAX_VSIMMS 4
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#define ESCC_CLOCK 4915200
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struct sun4m_hwdef {
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hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
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hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
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hwaddr serial_base, fd_base;
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hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
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hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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hwaddr bpp_base, dbri_base, sx_base;
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struct {
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hwaddr reg_base, vram_base;
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} vsimm[MAX_VSIMMS];
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hwaddr ecc_base;
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uint64_t max_mem;
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uint32_t ecc_version;
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uint32_t iommu_version;
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uint16_t machine_id;
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uint8_t nvram_machine_id;
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};
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void DMA_init(ISABus *bus, int high_page_enable)
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{
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}
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static void nvram_init(Nvram *nvram, uint8_t *macaddr,
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const char *cmdline, const char *boot_devices,
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ram_addr_t RAM_size, uint32_t kernel_size,
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int width, int height, int depth,
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int nvram_machine_id, const char *arch)
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{
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unsigned int i;
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int sysp_end;
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uint8_t image[0x1ff0];
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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memset(image, '\0', sizeof(image));
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/* OpenBIOS nvram variables partition */
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sysp_end = chrp_nvram_create_system_partition(image, 0);
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/* Free space partition */
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chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
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nvram_machine_id);
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for (i = 0; i < sizeof(image); i++) {
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(k->write)(nvram, i, image[i]);
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}
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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cs = CPU(sparc_env_get_cpu(env));
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trace_sun4m_cpu_interrupt(i);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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cs = CPU(sparc_env_get_cpu(env));
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trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUSPARCState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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cs->halted = 0;
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cpu_check_irqs(env);
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qemu_cpu_kick(cs);
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}
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static void cpu_set_irq(void *opaque, int irq, int level)
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{
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SPARCCPU *cpu = opaque;
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CPUSPARCState *env = &cpu->env;
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if (level) {
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trace_sun4m_cpu_set_irq_raise(irq);
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env->pil_in |= 1 << irq;
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cpu_kick_irq(cpu);
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} else {
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trace_sun4m_cpu_set_irq_lower(irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env);
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}
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}
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static void dummy_cpu_set_irq(void *opaque, int irq, int level)
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{
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}
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static void main_cpu_reset(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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cs->halted = 0;
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}
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static void secondary_cpu_reset(void *opaque)
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{
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SPARCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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cs->halted = 1;
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}
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static void cpu_halt_signal(void *opaque, int irq, int level)
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{
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if (level && current_cpu) {
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cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
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}
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}
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return addr - 0xf0000000ULL;
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}
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static unsigned long sun4m_load_kernel(const char *kernel_filename,
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const char *initrd_filename,
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ram_addr_t RAM_size)
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{
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int linux_boot;
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unsigned int i;
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long initrd_size, kernel_size;
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uint8_t *ptr;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
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TARGET_PAGE_SIZE);
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename,
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INITRD_LOAD_ADDR,
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RAM_size - INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
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if (ldl_p(ptr) == 0x48647253) { // HdrS
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stl_p(ptr + 16, INITRD_LOAD_ADDR);
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stl_p(ptr + 20, initrd_size);
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break;
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}
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}
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}
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}
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return kernel_size;
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}
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static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
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qdev_prop_set_uint32(dev, "version", version);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, addr);
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return s;
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}
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static void *sparc32_dma_init(hwaddr dma_base,
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hwaddr esp_base, qemu_irq espdma_irq,
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hwaddr le_base, qemu_irq ledma_irq)
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{
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DeviceState *dma;
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ESPDMADeviceState *espdma;
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LEDMADeviceState *ledma;
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SysBusESPState *esp;
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SysBusPCNetState *lance;
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dma = qdev_create(NULL, TYPE_SPARC32_DMA);
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qdev_init_nofail(dma);
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sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
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espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
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OBJECT(dma), "espdma"));
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sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
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esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
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sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
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ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
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OBJECT(dma), "ledma"));
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sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
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lance = SYSBUS_PCNET(object_resolve_path_component(
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OBJECT(ledma), "lance"));
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sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
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return dma;
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}
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static DeviceState *slavio_intctl_init(hwaddr addr,
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hwaddr addrg,
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qemu_irq **parent_irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i, j;
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dev = qdev_create(NULL, "slavio_intctl");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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for (i = 0; i < MAX_CPUS; i++) {
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for (j = 0; j < MAX_PILS; j++) {
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sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
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}
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}
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sysbus_mmio_map(s, 0, addrg);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
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}
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return dev;
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}
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#define SYS_TIMER_OFFSET 0x10000ULL
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#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
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static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
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qemu_irq *cpu_irqs, unsigned int num_cpus)
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{
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DeviceState *dev;
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SysBusDevice *s;
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unsigned int i;
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dev = qdev_create(NULL, "slavio_timer");
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qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, master_irq);
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sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
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for (i = 0; i < MAX_CPUS; i++) {
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sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
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sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
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}
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}
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static qemu_irq slavio_system_powerdown;
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static void slavio_powerdown_req(Notifier *n, void *opaque)
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{
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qemu_irq_raise(slavio_system_powerdown);
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}
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static Notifier slavio_system_powerdown_notifier = {
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.notify = slavio_powerdown_req
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};
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#define MISC_LEDS 0x01600000
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#define MISC_CFG 0x01800000
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#define MISC_DIAG 0x01a00000
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#define MISC_MDM 0x01b00000
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#define MISC_SYS 0x01f00000
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static void slavio_misc_init(hwaddr base,
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hwaddr aux1_base,
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hwaddr aux2_base, qemu_irq irq,
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qemu_irq fdc_tc)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "slavio_misc");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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if (base) {
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/* 8 bit registers */
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/* Slavio control */
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sysbus_mmio_map(s, 0, base + MISC_CFG);
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/* Diagnostics */
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sysbus_mmio_map(s, 1, base + MISC_DIAG);
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/* Modem control */
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sysbus_mmio_map(s, 2, base + MISC_MDM);
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/* 16 bit registers */
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/* ss600mp diag LEDs */
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sysbus_mmio_map(s, 3, base + MISC_LEDS);
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/* 32 bit registers */
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/* System control */
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sysbus_mmio_map(s, 4, base + MISC_SYS);
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}
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if (aux1_base) {
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/* AUX 1 (Misc System Functions) */
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sysbus_mmio_map(s, 5, aux1_base);
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}
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if (aux2_base) {
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/* AUX 2 (Software Powerdown Control) */
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sysbus_mmio_map(s, 6, aux2_base);
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}
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sysbus_connect_irq(s, 0, irq);
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sysbus_connect_irq(s, 1, fdc_tc);
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slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
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qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
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}
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static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "eccmemctl");
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qdev_prop_set_uint32(dev, "version", version);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, irq);
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sysbus_mmio_map(s, 0, base);
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if (version == 0) { // SS-600MP only
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sysbus_mmio_map(s, 1, base + 0x1000);
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}
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}
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static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "apc");
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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/* Power management (APC) XXX: not a Slavio device */
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sysbus_mmio_map(s, 0, power_base);
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sysbus_connect_irq(s, 0, cpu_halt);
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}
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|
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static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
|
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int height, int depth)
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{
|
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DeviceState *dev;
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SysBusDevice *s;
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|
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dev = qdev_create(NULL, "SUNW,tcx");
|
|
qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
|
qdev_prop_set_uint16(dev, "width", width);
|
|
qdev_prop_set_uint16(dev, "height", height);
|
|
qdev_prop_set_uint16(dev, "depth", depth);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
/* 10/ROM : FCode ROM */
|
|
sysbus_mmio_map(s, 0, addr);
|
|
/* 2/STIP : Stipple */
|
|
sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
|
|
/* 3/BLIT : Blitter */
|
|
sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
|
|
/* 5/RSTIP : Raw Stipple */
|
|
sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
|
|
/* 6/RBLIT : Raw Blitter */
|
|
sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
|
|
/* 7/TEC : Transform Engine */
|
|
sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
|
|
/* 8/CMAP : DAC */
|
|
sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
|
|
/* 9/THC : */
|
|
if (depth == 8) {
|
|
sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
|
|
} else {
|
|
sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
|
|
}
|
|
/* 11/DHC : */
|
|
sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
|
|
/* 12/ALT : */
|
|
sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
|
|
/* 0/DFB8 : 8-bit plane */
|
|
sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
|
|
/* 1/DFB24 : 24bit plane */
|
|
sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
|
|
/* 4/RDFB32: Raw framebuffer. Control plane */
|
|
sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
|
|
/* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
|
|
if (depth == 8) {
|
|
sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
|
|
}
|
|
|
|
sysbus_connect_irq(s, 0, irq);
|
|
}
|
|
|
|
static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
|
|
int height, int depth)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
|
|
dev = qdev_create(NULL, "cgthree");
|
|
qdev_prop_set_uint32(dev, "vram-size", vram_size);
|
|
qdev_prop_set_uint16(dev, "width", width);
|
|
qdev_prop_set_uint16(dev, "height", height);
|
|
qdev_prop_set_uint16(dev, "depth", depth);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
/* FCode ROM */
|
|
sysbus_mmio_map(s, 0, addr);
|
|
/* DAC */
|
|
sysbus_mmio_map(s, 1, addr + 0x400000ULL);
|
|
/* 8-bit plane */
|
|
sysbus_mmio_map(s, 2, addr + 0x800000ULL);
|
|
|
|
sysbus_connect_irq(s, 0, irq);
|
|
}
|
|
|
|
/* NCR89C100/MACIO Internal ID register */
|
|
|
|
#define TYPE_MACIO_ID_REGISTER "macio_idreg"
|
|
|
|
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
|
|
|
|
static void idreg_init(hwaddr addr)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
|
|
dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
cpu_physical_memory_write_rom(&address_space_memory,
|
|
addr, idreg_data, sizeof(idreg_data));
|
|
}
|
|
|
|
#define MACIO_ID_REGISTER(obj) \
|
|
OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
|
|
|
|
typedef struct IDRegState {
|
|
SysBusDevice parent_obj;
|
|
|
|
MemoryRegion mem;
|
|
} IDRegState;
|
|
|
|
static void idreg_init1(Object *obj)
|
|
{
|
|
IDRegState *s = MACIO_ID_REGISTER(obj);
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
|
|
memory_region_init_ram_nomigrate(&s->mem, obj,
|
|
"sun4m.idreg", sizeof(idreg_data), &error_fatal);
|
|
vmstate_register_ram_global(&s->mem);
|
|
memory_region_set_readonly(&s->mem, true);
|
|
sysbus_init_mmio(dev, &s->mem);
|
|
}
|
|
|
|
static const TypeInfo idreg_info = {
|
|
.name = TYPE_MACIO_ID_REGISTER,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(IDRegState),
|
|
.instance_init = idreg_init1,
|
|
};
|
|
|
|
#define TYPE_TCX_AFX "tcx_afx"
|
|
#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
|
|
|
|
typedef struct AFXState {
|
|
SysBusDevice parent_obj;
|
|
|
|
MemoryRegion mem;
|
|
} AFXState;
|
|
|
|
/* SS-5 TCX AFX register */
|
|
static void afx_init(hwaddr addr)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
|
|
dev = qdev_create(NULL, TYPE_TCX_AFX);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
}
|
|
|
|
static void afx_init1(Object *obj)
|
|
{
|
|
AFXState *s = TCX_AFX(obj);
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
|
|
memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
|
|
vmstate_register_ram_global(&s->mem);
|
|
sysbus_init_mmio(dev, &s->mem);
|
|
}
|
|
|
|
static const TypeInfo afx_info = {
|
|
.name = TYPE_TCX_AFX,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(AFXState),
|
|
.instance_init = afx_init1,
|
|
};
|
|
|
|
#define TYPE_OPENPROM "openprom"
|
|
#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
|
|
|
|
typedef struct PROMState {
|
|
SysBusDevice parent_obj;
|
|
|
|
MemoryRegion prom;
|
|
} PROMState;
|
|
|
|
/* Boot PROM (OpenBIOS) */
|
|
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
|
|
{
|
|
hwaddr *base_addr = (hwaddr *)opaque;
|
|
return addr + *base_addr - PROM_VADDR;
|
|
}
|
|
|
|
static void prom_init(hwaddr addr, const char *bios_name)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
char *filename;
|
|
int ret;
|
|
|
|
dev = qdev_create(NULL, TYPE_OPENPROM);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
|
|
/* load boot prom */
|
|
if (bios_name == NULL) {
|
|
bios_name = PROM_FILENAME;
|
|
}
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
if (filename) {
|
|
ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
|
NULL, NULL, 1, EM_SPARC, 0, 0);
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
|
|
}
|
|
g_free(filename);
|
|
} else {
|
|
ret = -1;
|
|
}
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
static void prom_init1(Object *obj)
|
|
{
|
|
PROMState *s = OPENPROM(obj);
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
|
|
memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
|
|
&error_fatal);
|
|
vmstate_register_ram_global(&s->prom);
|
|
memory_region_set_readonly(&s->prom, true);
|
|
sysbus_init_mmio(dev, &s->prom);
|
|
}
|
|
|
|
static Property prom_properties[] = {
|
|
{/* end of property list */},
|
|
};
|
|
|
|
static void prom_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->props = prom_properties;
|
|
}
|
|
|
|
static const TypeInfo prom_info = {
|
|
.name = TYPE_OPENPROM,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PROMState),
|
|
.class_init = prom_class_init,
|
|
.instance_init = prom_init1,
|
|
};
|
|
|
|
#define TYPE_SUN4M_MEMORY "memory"
|
|
#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
|
|
|
|
typedef struct RamDevice {
|
|
SysBusDevice parent_obj;
|
|
|
|
MemoryRegion ram;
|
|
uint64_t size;
|
|
} RamDevice;
|
|
|
|
/* System RAM */
|
|
static void ram_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
RamDevice *d = SUN4M_RAM(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
|
|
d->size);
|
|
sysbus_init_mmio(sbd, &d->ram);
|
|
}
|
|
|
|
static void ram_init(hwaddr addr, ram_addr_t RAM_size,
|
|
uint64_t max_mem)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
RamDevice *d;
|
|
|
|
/* allocate RAM */
|
|
if ((uint64_t)RAM_size > max_mem) {
|
|
fprintf(stderr,
|
|
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
|
(unsigned int)(RAM_size / (1024 * 1024)),
|
|
(unsigned int)(max_mem / (1024 * 1024)));
|
|
exit(1);
|
|
}
|
|
dev = qdev_create(NULL, "memory");
|
|
s = SYS_BUS_DEVICE(dev);
|
|
|
|
d = SUN4M_RAM(dev);
|
|
d->size = RAM_size;
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
}
|
|
|
|
static Property ram_properties[] = {
|
|
DEFINE_PROP_UINT64("size", RamDevice, size, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ram_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = ram_realize;
|
|
dc->props = ram_properties;
|
|
}
|
|
|
|
static const TypeInfo ram_info = {
|
|
.name = TYPE_SUN4M_MEMORY,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(RamDevice),
|
|
.class_init = ram_class_init,
|
|
};
|
|
|
|
static void cpu_devinit(const char *cpu_type, unsigned int id,
|
|
uint64_t prom_addr, qemu_irq **cpu_irqs)
|
|
{
|
|
CPUState *cs;
|
|
SPARCCPU *cpu;
|
|
CPUSPARCState *env;
|
|
|
|
cpu = SPARC_CPU(cpu_create(cpu_type));
|
|
env = &cpu->env;
|
|
|
|
cpu_sparc_set_id(env, id);
|
|
if (id == 0) {
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
} else {
|
|
qemu_register_reset(secondary_cpu_reset, cpu);
|
|
cs = CPU(cpu);
|
|
cs->halted = 1;
|
|
}
|
|
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
|
|
env->prom_addr = prom_addr;
|
|
}
|
|
|
|
static void dummy_fdc_tc(void *opaque, int irq, int level)
|
|
{
|
|
}
|
|
|
|
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
|
MachineState *machine)
|
|
{
|
|
DeviceState *slavio_intctl;
|
|
unsigned int i;
|
|
void *nvram;
|
|
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
|
|
qemu_irq fdc_tc;
|
|
unsigned long kernel_size;
|
|
DriveInfo *fd[MAX_FD];
|
|
FWCfgState *fw_cfg;
|
|
unsigned int num_vsimms;
|
|
|
|
/* init CPUs */
|
|
for(i = 0; i < smp_cpus; i++) {
|
|
cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
|
|
}
|
|
|
|
for (i = smp_cpus; i < MAX_CPUS; i++)
|
|
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
|
|
|
|
|
/* set up devices */
|
|
ram_init(0, machine->ram_size, hwdef->max_mem);
|
|
/* models without ECC don't trap when missing ram is accessed */
|
|
if (!hwdef->ecc_base) {
|
|
empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
|
|
}
|
|
|
|
prom_init(hwdef->slavio_base, bios_name);
|
|
|
|
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
|
|
hwdef->intctl_base + 0x10000ULL,
|
|
cpu_irqs);
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
|
|
}
|
|
for (i = 0; i < MAX_CPUS; i++) {
|
|
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
|
}
|
|
|
|
if (hwdef->idreg_base) {
|
|
idreg_init(hwdef->idreg_base);
|
|
}
|
|
|
|
if (hwdef->afx_base) {
|
|
afx_init(hwdef->afx_base);
|
|
}
|
|
|
|
iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
|
|
|
|
if (hwdef->iommu_pad_base) {
|
|
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
|
Software shouldn't use aliased addresses, neither should it crash
|
|
when does. Using empty_slot instead of aliasing can help with
|
|
debugging such accesses */
|
|
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
|
|
}
|
|
|
|
sparc32_dma_init(hwdef->dma_base,
|
|
hwdef->esp_base, slavio_irq[18],
|
|
hwdef->le_base, slavio_irq[16]);
|
|
|
|
if (graphic_depth != 8 && graphic_depth != 24) {
|
|
error_report("Unsupported depth: %d", graphic_depth);
|
|
exit (1);
|
|
}
|
|
num_vsimms = 0;
|
|
if (num_vsimms == 0) {
|
|
if (vga_interface_type == VGA_CG3) {
|
|
if (graphic_depth != 8) {
|
|
error_report("Unsupported depth: %d", graphic_depth);
|
|
exit(1);
|
|
}
|
|
|
|
if (!(graphic_width == 1024 && graphic_height == 768) &&
|
|
!(graphic_width == 1152 && graphic_height == 900)) {
|
|
error_report("Unsupported resolution: %d x %d", graphic_width,
|
|
graphic_height);
|
|
exit(1);
|
|
}
|
|
|
|
/* sbus irq 5 */
|
|
cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
} else {
|
|
/* If no display specified, default to TCX */
|
|
if (graphic_depth != 8 && graphic_depth != 24) {
|
|
error_report("Unsupported depth: %d", graphic_depth);
|
|
exit(1);
|
|
}
|
|
|
|
if (!(graphic_width == 1024 && graphic_height == 768)) {
|
|
error_report("Unsupported resolution: %d x %d",
|
|
graphic_width, graphic_height);
|
|
exit(1);
|
|
}
|
|
|
|
tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
|
|
graphic_width, graphic_height, graphic_depth);
|
|
}
|
|
}
|
|
|
|
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
|
/* vsimm registers probed by OBP */
|
|
if (hwdef->vsimm[i].reg_base) {
|
|
empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
|
|
}
|
|
}
|
|
|
|
if (hwdef->sx_base) {
|
|
empty_slot_init(hwdef->sx_base, 0x2000);
|
|
}
|
|
|
|
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
|
|
|
|
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
|
|
|
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
|
!machine->enable_graphics, ESCC_CLOCK, 1);
|
|
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
|
|
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
|
|
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
|
|
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
|
|
|
|
if (hwdef->apc_base) {
|
|
apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
|
|
}
|
|
|
|
if (hwdef->fd_base) {
|
|
/* there is zero or one floppy drive */
|
|
memset(fd, 0, sizeof(fd));
|
|
fd[0] = drive_get(IF_FLOPPY, 0, 0);
|
|
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
|
&fdc_tc);
|
|
} else {
|
|
fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
|
|
}
|
|
|
|
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
|
|
slavio_irq[30], fdc_tc);
|
|
|
|
if (hwdef->cs_base) {
|
|
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
|
slavio_irq[5]);
|
|
}
|
|
|
|
if (hwdef->dbri_base) {
|
|
/* ISDN chip with attached CS4215 audio codec */
|
|
/* prom space */
|
|
empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
|
|
/* reg space */
|
|
empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
|
|
}
|
|
|
|
if (hwdef->bpp_base) {
|
|
/* parallel port */
|
|
empty_slot_init(hwdef->bpp_base, 0x20);
|
|
}
|
|
|
|
kernel_size = sun4m_load_kernel(machine->kernel_filename,
|
|
machine->initrd_filename,
|
|
machine->ram_size);
|
|
|
|
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
|
|
machine->boot_order, machine->ram_size, kernel_size,
|
|
graphic_width, graphic_height, graphic_depth,
|
|
hwdef->nvram_machine_id, "Sun4m");
|
|
|
|
if (hwdef->ecc_base)
|
|
ecc_init(hwdef->ecc_base, slavio_irq[28],
|
|
hwdef->ecc_version);
|
|
|
|
fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
if (machine->kernel_cmdline) {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
|
|
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
|
|
machine->kernel_cmdline);
|
|
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
|
strlen(machine->kernel_cmdline) + 1);
|
|
} else {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
|
}
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
|
}
|
|
|
|
enum {
|
|
ss5_id = 32,
|
|
vger_id,
|
|
lx_id,
|
|
ss4_id,
|
|
scls_id,
|
|
sbook_id,
|
|
ss10_id = 64,
|
|
ss20_id,
|
|
ss600mp_id,
|
|
};
|
|
|
|
static const struct sun4m_hwdef sun4m_hwdefs[] = {
|
|
/* SS-5 */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.iommu_pad_base = 0x10004000,
|
|
.iommu_pad_len = 0x0fffb000,
|
|
.tcx_base = 0x50000000,
|
|
.cs_base = 0x6c000000,
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.apc_base = 0x6a000000,
|
|
.afx_base = 0x6e000000,
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = ss5_id,
|
|
.iommu_version = 0x05000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
/* SS-10 */
|
|
{
|
|
.iommu_base = 0xfe0000000ULL,
|
|
.tcx_base = 0xe20000000ULL,
|
|
.slavio_base = 0xff0000000ULL,
|
|
.ms_kb_base = 0xff1000000ULL,
|
|
.serial_base = 0xff1100000ULL,
|
|
.nvram_base = 0xff1200000ULL,
|
|
.fd_base = 0xff1700000ULL,
|
|
.counter_base = 0xff1300000ULL,
|
|
.intctl_base = 0xff1400000ULL,
|
|
.idreg_base = 0xef0000000ULL,
|
|
.dma_base = 0xef0400000ULL,
|
|
.esp_base = 0xef0800000ULL,
|
|
.le_base = 0xef0c00000ULL,
|
|
.apc_base = 0xefa000000ULL, // XXX should not exist
|
|
.aux1_base = 0xff1800000ULL,
|
|
.aux2_base = 0xff1a01000ULL,
|
|
.ecc_base = 0xf00000000ULL,
|
|
.ecc_version = 0x10000000, // version 0, implementation 1
|
|
.nvram_machine_id = 0x72,
|
|
.machine_id = ss10_id,
|
|
.iommu_version = 0x03000000,
|
|
.max_mem = 0xf00000000ULL,
|
|
},
|
|
/* SS-600MP */
|
|
{
|
|
.iommu_base = 0xfe0000000ULL,
|
|
.tcx_base = 0xe20000000ULL,
|
|
.slavio_base = 0xff0000000ULL,
|
|
.ms_kb_base = 0xff1000000ULL,
|
|
.serial_base = 0xff1100000ULL,
|
|
.nvram_base = 0xff1200000ULL,
|
|
.counter_base = 0xff1300000ULL,
|
|
.intctl_base = 0xff1400000ULL,
|
|
.dma_base = 0xef0081000ULL,
|
|
.esp_base = 0xef0080000ULL,
|
|
.le_base = 0xef0060000ULL,
|
|
.apc_base = 0xefa000000ULL, // XXX should not exist
|
|
.aux1_base = 0xff1800000ULL,
|
|
.aux2_base = 0xff1a01000ULL, // XXX should not exist
|
|
.ecc_base = 0xf00000000ULL,
|
|
.ecc_version = 0x00000000, // version 0, implementation 0
|
|
.nvram_machine_id = 0x71,
|
|
.machine_id = ss600mp_id,
|
|
.iommu_version = 0x01000000,
|
|
.max_mem = 0xf00000000ULL,
|
|
},
|
|
/* SS-20 */
|
|
{
|
|
.iommu_base = 0xfe0000000ULL,
|
|
.tcx_base = 0xe20000000ULL,
|
|
.slavio_base = 0xff0000000ULL,
|
|
.ms_kb_base = 0xff1000000ULL,
|
|
.serial_base = 0xff1100000ULL,
|
|
.nvram_base = 0xff1200000ULL,
|
|
.fd_base = 0xff1700000ULL,
|
|
.counter_base = 0xff1300000ULL,
|
|
.intctl_base = 0xff1400000ULL,
|
|
.idreg_base = 0xef0000000ULL,
|
|
.dma_base = 0xef0400000ULL,
|
|
.esp_base = 0xef0800000ULL,
|
|
.le_base = 0xef0c00000ULL,
|
|
.bpp_base = 0xef4800000ULL,
|
|
.apc_base = 0xefa000000ULL, // XXX should not exist
|
|
.aux1_base = 0xff1800000ULL,
|
|
.aux2_base = 0xff1a01000ULL,
|
|
.dbri_base = 0xee0000000ULL,
|
|
.sx_base = 0xf80000000ULL,
|
|
.vsimm = {
|
|
{
|
|
.reg_base = 0x9c000000ULL,
|
|
.vram_base = 0xfc000000ULL
|
|
}, {
|
|
.reg_base = 0x90000000ULL,
|
|
.vram_base = 0xf0000000ULL
|
|
}, {
|
|
.reg_base = 0x94000000ULL
|
|
}, {
|
|
.reg_base = 0x98000000ULL
|
|
}
|
|
},
|
|
.ecc_base = 0xf00000000ULL,
|
|
.ecc_version = 0x20000000, // version 0, implementation 2
|
|
.nvram_machine_id = 0x72,
|
|
.machine_id = ss20_id,
|
|
.iommu_version = 0x13000000,
|
|
.max_mem = 0xf00000000ULL,
|
|
},
|
|
/* Voyager */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.tcx_base = 0x50000000,
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.apc_base = 0x71300000, // pmc
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = vger_id,
|
|
.iommu_version = 0x05000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
/* LX */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.iommu_pad_base = 0x10004000,
|
|
.iommu_pad_len = 0x0fffb000,
|
|
.tcx_base = 0x50000000,
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = lx_id,
|
|
.iommu_version = 0x04000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
/* SS-4 */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.tcx_base = 0x50000000,
|
|
.cs_base = 0x6c000000,
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.apc_base = 0x6a000000,
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = ss4_id,
|
|
.iommu_version = 0x05000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
/* SPARCClassic */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.tcx_base = 0x50000000,
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.apc_base = 0x6a000000,
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = scls_id,
|
|
.iommu_version = 0x05000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
/* SPARCbook */
|
|
{
|
|
.iommu_base = 0x10000000,
|
|
.tcx_base = 0x50000000, // XXX
|
|
.slavio_base = 0x70000000,
|
|
.ms_kb_base = 0x71000000,
|
|
.serial_base = 0x71100000,
|
|
.nvram_base = 0x71200000,
|
|
.fd_base = 0x71400000,
|
|
.counter_base = 0x71d00000,
|
|
.intctl_base = 0x71e00000,
|
|
.idreg_base = 0x78000000,
|
|
.dma_base = 0x78400000,
|
|
.esp_base = 0x78800000,
|
|
.le_base = 0x78c00000,
|
|
.apc_base = 0x6a000000,
|
|
.aux1_base = 0x71900000,
|
|
.aux2_base = 0x71910000,
|
|
.nvram_machine_id = 0x80,
|
|
.machine_id = sbook_id,
|
|
.iommu_version = 0x05000000,
|
|
.max_mem = 0x10000000,
|
|
},
|
|
};
|
|
|
|
/* SPARCstation 5 hardware initialisation */
|
|
static void ss5_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[0], machine);
|
|
}
|
|
|
|
/* SPARCstation 10 hardware initialisation */
|
|
static void ss10_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[1], machine);
|
|
}
|
|
|
|
/* SPARCserver 600MP hardware initialisation */
|
|
static void ss600mp_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[2], machine);
|
|
}
|
|
|
|
/* SPARCstation 20 hardware initialisation */
|
|
static void ss20_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[3], machine);
|
|
}
|
|
|
|
/* SPARCstation Voyager hardware initialisation */
|
|
static void vger_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[4], machine);
|
|
}
|
|
|
|
/* SPARCstation LX hardware initialisation */
|
|
static void ss_lx_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[5], machine);
|
|
}
|
|
|
|
/* SPARCstation 4 hardware initialisation */
|
|
static void ss4_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[6], machine);
|
|
}
|
|
|
|
/* SPARCClassic hardware initialisation */
|
|
static void scls_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[7], machine);
|
|
}
|
|
|
|
/* SPARCbook hardware initialisation */
|
|
static void sbook_init(MachineState *machine)
|
|
{
|
|
sun4m_hw_init(&sun4m_hwdefs[8], machine);
|
|
}
|
|
|
|
static void ss5_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation 5";
|
|
mc->init = ss5_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->is_default = 1;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
|
}
|
|
|
|
static const TypeInfo ss5_type = {
|
|
.name = MACHINE_TYPE_NAME("SS-5"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss5_class_init,
|
|
};
|
|
|
|
static void ss10_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation 10";
|
|
mc->init = ss10_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->max_cpus = 4;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
|
}
|
|
|
|
static const TypeInfo ss10_type = {
|
|
.name = MACHINE_TYPE_NAME("SS-10"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss10_class_init,
|
|
};
|
|
|
|
static void ss600mp_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCserver 600MP";
|
|
mc->init = ss600mp_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->max_cpus = 4;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
|
}
|
|
|
|
static const TypeInfo ss600mp_type = {
|
|
.name = MACHINE_TYPE_NAME("SS-600MP"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss600mp_class_init,
|
|
};
|
|
|
|
static void ss20_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation 20";
|
|
mc->init = ss20_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->max_cpus = 4;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
|
}
|
|
|
|
static const TypeInfo ss20_type = {
|
|
.name = MACHINE_TYPE_NAME("SS-20"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss20_class_init,
|
|
};
|
|
|
|
static void voyager_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation Voyager";
|
|
mc->init = vger_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
|
}
|
|
|
|
static const TypeInfo voyager_type = {
|
|
.name = MACHINE_TYPE_NAME("Voyager"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = voyager_class_init,
|
|
};
|
|
|
|
static void ss_lx_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation LX";
|
|
mc->init = ss_lx_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
|
}
|
|
|
|
static const TypeInfo ss_lx_type = {
|
|
.name = MACHINE_TYPE_NAME("LX"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss_lx_class_init,
|
|
};
|
|
|
|
static void ss4_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCstation 4";
|
|
mc->init = ss4_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
|
}
|
|
|
|
static const TypeInfo ss4_type = {
|
|
.name = MACHINE_TYPE_NAME("SS-4"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = ss4_class_init,
|
|
};
|
|
|
|
static void scls_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCClassic";
|
|
mc->init = scls_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
|
}
|
|
|
|
static const TypeInfo scls_type = {
|
|
.name = MACHINE_TYPE_NAME("SPARCClassic"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = scls_class_init,
|
|
};
|
|
|
|
static void sbook_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4m platform, SPARCbook";
|
|
mc->init = sbook_init;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
|
}
|
|
|
|
static const TypeInfo sbook_type = {
|
|
.name = MACHINE_TYPE_NAME("SPARCbook"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = sbook_class_init,
|
|
};
|
|
|
|
static void sun4m_register_types(void)
|
|
{
|
|
type_register_static(&idreg_info);
|
|
type_register_static(&afx_info);
|
|
type_register_static(&prom_info);
|
|
type_register_static(&ram_info);
|
|
|
|
type_register_static(&ss5_type);
|
|
type_register_static(&ss10_type);
|
|
type_register_static(&ss600mp_type);
|
|
type_register_static(&ss20_type);
|
|
type_register_static(&voyager_type);
|
|
type_register_static(&ss_lx_type);
|
|
type_register_static(&ss4_type);
|
|
type_register_static(&scls_type);
|
|
type_register_static(&sbook_type);
|
|
}
|
|
|
|
type_init(sun4m_register_types)
|