mirror of https://gitee.com/openkylin/qemu.git
746 lines
23 KiB
C
746 lines
23 KiB
C
/*
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* High Precisition Event Timer emulation
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*
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* Copyright (c) 2007 Alexander Graf
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* Copyright (c) 2008 IBM Corporation
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*
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* Authors: Beth Kon <bkon@us.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* *****************************************************************
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*
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* This driver attempts to emulate an HPET device in software.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "console.h"
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#include "qemu-timer.h"
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#include "hpet_emul.h"
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#include "sysbus.h"
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#include "mc146818rtc.h"
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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#define HPET_MSI_SUPPORT 0
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struct HPETState;
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typedef struct HPETTimer { /* timers */
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uint8_t tn; /*timer number*/
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QEMUTimer *qemu_timer;
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struct HPETState *state;
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/* Memory-mapped, software visible timer registers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route */
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/* Hidden register state */
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uint64_t period; /* Last value written to comparator */
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
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* mode. Next pop will be actual timer expiration.
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*/
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} HPETTimer;
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typedef struct HPETState {
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SysBusDevice busdev;
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uint64_t hpet_offset;
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qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
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uint32_t flags;
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uint8_t rtc_irq_level;
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uint8_t num_timers;
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HPETTimer timer[HPET_MAX_TIMERS];
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t config; /* configuration */
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uint64_t isr; /* interrupt status reg */
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uint64_t hpet_counter; /* main counter */
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uint8_t hpet_id; /* instance id */
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} HPETState;
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static uint32_t hpet_in_legacy_mode(HPETState *s)
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{
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return s->config & HPET_CFG_LEGACY;
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}
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static uint32_t timer_int_route(struct HPETTimer *timer)
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{
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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}
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static uint32_t timer_fsb_route(HPETTimer *t)
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{
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return t->config & HPET_TN_FSB_ENABLE;
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}
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static uint32_t hpet_enabled(HPETState *s)
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{
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return s->config & HPET_CFG_ENABLE;
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}
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static uint32_t timer_is_periodic(HPETTimer *t)
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{
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return t->config & HPET_TN_PERIODIC;
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}
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static uint32_t timer_enabled(HPETTimer *t)
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{
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return t->config & HPET_TN_ENABLE;
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}
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static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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{
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return ((int32_t)(b) - (int32_t)(a) < 0);
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}
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static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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{
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return ((int64_t)(b) - (int64_t)(a) < 0);
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}
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static uint64_t ticks_to_ns(uint64_t value)
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{
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return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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}
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static uint64_t ns_to_ticks(uint64_t value)
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{
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return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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}
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static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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{
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new &= mask;
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new |= old & ~mask;
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return new;
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}
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static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
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{
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return (!(old & mask) && (new & mask));
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}
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static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
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{
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return ((old & mask) && !(new & mask));
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}
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static uint64_t hpet_get_ticks(HPETState *s)
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{
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return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
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}
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/*
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* calculate diff between comparator value and current ticks
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*/
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static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
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{
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp;
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cmp = (uint32_t)t->cmp;
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diff = cmp - (uint32_t)current;
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diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp;
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cmp = t->cmp;
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diff = cmp - current;
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diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
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return diff;
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}
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}
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static void update_irq(struct HPETTimer *timer, int set)
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{
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uint64_t mask;
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HPETState *s;
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
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/* if LegacyReplacementRoute bit is set, HPET specification requires
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
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} else {
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route = timer_int_route(timer);
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}
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s = timer->state;
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mask = 1 << timer->tn;
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if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
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s->isr &= ~mask;
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if (!timer_fsb_route(timer)) {
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qemu_irq_lower(s->irqs[route]);
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}
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} else if (timer_fsb_route(timer)) {
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stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
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} else if (timer->config & HPET_TN_TYPE_LEVEL) {
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s->isr |= mask;
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qemu_irq_raise(s->irqs[route]);
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} else {
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s->isr &= ~mask;
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qemu_irq_pulse(s->irqs[route]);
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}
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}
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static void hpet_pre_save(void *opaque)
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{
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HPETState *s = opaque;
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks(s);
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}
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static int hpet_pre_load(void *opaque)
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{
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HPETState *s = opaque;
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/* version 1 only supports 3, later versions will load the actual value */
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s->num_timers = HPET_MIN_TIMERS;
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return 0;
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}
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static int hpet_post_load(void *opaque, int version_id)
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{
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HPETState *s = opaque;
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/* Recalculate the offset between the main counter and guest time */
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s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
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/* Push number of timers into capability returned via HPET_ID */
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s->capability &= ~HPET_ID_NUM_TIM_MASK;
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s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
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hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
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/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
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s->flags &= ~(1 << HPET_MSI_SUPPORT);
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if (s->timer[0].config & HPET_TN_FSB_CAP) {
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s->flags |= 1 << HPET_MSI_SUPPORT;
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}
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return 0;
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}
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static const VMStateDescription vmstate_hpet_timer = {
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.name = "hpet_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(tn, HPETTimer),
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VMSTATE_UINT64(config, HPETTimer),
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VMSTATE_UINT64(cmp, HPETTimer),
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VMSTATE_UINT64(fsb, HPETTimer),
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VMSTATE_UINT64(period, HPETTimer),
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VMSTATE_UINT8(wrap_flag, HPETTimer),
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VMSTATE_TIMER(qemu_timer, HPETTimer),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_hpet = {
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.name = "hpet",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = hpet_pre_save,
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.pre_load = hpet_pre_load,
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.post_load = hpet_post_load,
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.fields = (VMStateField []) {
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VMSTATE_UINT64(config, HPETState),
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VMSTATE_UINT64(isr, HPETState),
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VMSTATE_UINT64(hpet_counter, HPETState),
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VMSTATE_UINT8_V(num_timers, HPETState, 2),
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VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
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vmstate_hpet_timer, HPETTimer),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* timer expiration callback
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*/
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static void hpet_timer(void *opaque)
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{
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HPETTimer *t = opaque;
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uint64_t diff;
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uint64_t period = t->period;
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uint64_t cur_tick = hpet_get_ticks(t->state);
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if (timer_is_periodic(t) && period != 0) {
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp)) {
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t->cmp = (uint32_t)(t->cmp + t->period);
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}
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} else {
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while (hpet_time_after64(cur_tick, t->cmp)) {
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t->cmp += period;
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}
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}
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diff = hpet_calculate_diff(t, cur_tick);
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qemu_mod_timer(t->qemu_timer,
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qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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if (t->wrap_flag) {
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diff = hpet_calculate_diff(t, cur_tick);
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qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
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(int64_t)ticks_to_ns(diff));
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t->wrap_flag = 0;
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}
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}
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update_irq(t, 1);
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}
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static void hpet_set_timer(HPETTimer *t)
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{
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uint64_t diff;
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uint32_t wrap_diff; /* how many ticks until we wrap? */
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uint64_t cur_tick = hpet_get_ticks(t->state);
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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diff = hpet_calculate_diff(t, cur_tick);
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/* hpet spec says in one-shot 32-bit mode, generate an interrupt when
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* counter wraps in addition to an interrupt with comparator match.
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*/
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if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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if (wrap_diff < (uint32_t)diff) {
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diff = wrap_diff;
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t->wrap_flag = 1;
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}
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}
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qemu_mod_timer(t->qemu_timer,
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qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
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}
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static void hpet_del_timer(HPETTimer *t)
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{
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qemu_del_timer(t->qemu_timer);
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update_irq(t, 0);
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}
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#ifdef HPET_DEBUG
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static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
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{
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printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
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return 0;
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}
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static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
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{
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printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
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return 0;
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}
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#endif
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static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
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{
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HPETState *s = opaque;
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uint64_t cur_tick, index;
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
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index = addr;
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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HPETTimer *timer = &s->timer[timer_id];
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if (timer_id > s->num_timers) {
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DPRINTF("qemu: timer id out of range\n");
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return 0;
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}
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switch ((addr - 0x100) % 0x20) {
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case HPET_TN_CFG:
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return timer->config;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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return timer->config >> 32;
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case HPET_TN_CMP: // comparator register
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return timer->cmp;
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case HPET_TN_CMP + 4:
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return timer->cmp >> 32;
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case HPET_TN_ROUTE:
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return timer->fsb;
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case HPET_TN_ROUTE + 4:
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return timer->fsb >> 32;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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}
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} else {
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switch (index) {
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case HPET_ID:
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return s->capability;
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case HPET_PERIOD:
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return s->capability >> 32;
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case HPET_CFG:
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return s->config;
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case HPET_CFG + 4:
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0;
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case HPET_COUNTER:
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if (hpet_enabled(s)) {
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cur_tick = hpet_get_ticks(s);
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} else {
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cur_tick = s->hpet_counter;
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}
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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return cur_tick;
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case HPET_COUNTER + 4:
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if (hpet_enabled(s)) {
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cur_tick = hpet_get_ticks(s);
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} else {
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cur_tick = s->hpet_counter;
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}
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DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
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return cur_tick >> 32;
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case HPET_STATUS:
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return s->isr;
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default:
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break;
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}
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}
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return 0;
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}
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#ifdef HPET_DEBUG
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static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
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addr, value);
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}
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static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
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addr, value);
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}
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#endif
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static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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int i;
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HPETState *s = opaque;
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uint64_t old_val, new_val, val, index;
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DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
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index = addr;
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old_val = hpet_ram_readl(opaque, addr);
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new_val = value;
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/*address range of all TN regs*/
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if (index >= 0x100 && index <= 0x3ff) {
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uint8_t timer_id = (addr - 0x100) / 0x20;
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HPETTimer *timer = &s->timer[timer_id];
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DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
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if (timer_id > s->num_timers) {
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DPRINTF("qemu: timer id out of range\n");
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return;
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}
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switch ((addr - 0x100) % 0x20) {
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case HPET_TN_CFG:
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
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if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
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update_irq(timer, 0);
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}
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val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
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timer->config = (timer->config & 0xffffffff00000000ULL) | val;
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if (new_val & HPET_TN_32BIT) {
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timer->cmp = (uint32_t)timer->cmp;
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timer->period = (uint32_t)timer->period;
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}
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if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
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hpet_set_timer(timer);
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} else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
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hpet_del_timer(timer);
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}
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break;
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case HPET_TN_CFG + 4: // Interrupt capabilities
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DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
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break;
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case HPET_TN_CMP: // comparator register
|
|
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
|
if (timer->config & HPET_TN_32BIT) {
|
|
new_val = (uint32_t)new_val;
|
|
}
|
|
if (!timer_is_periodic(timer)
|
|
|| (timer->config & HPET_TN_SETVAL)) {
|
|
timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
|
|
}
|
|
if (timer_is_periodic(timer)) {
|
|
/*
|
|
* FIXME: Clamp period to reasonable min value?
|
|
* Clamp period to reasonable max value
|
|
*/
|
|
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
|
|
timer->period =
|
|
(timer->period & 0xffffffff00000000ULL) | new_val;
|
|
}
|
|
timer->config &= ~HPET_TN_SETVAL;
|
|
if (hpet_enabled(s)) {
|
|
hpet_set_timer(timer);
|
|
}
|
|
break;
|
|
case HPET_TN_CMP + 4: // comparator register high order
|
|
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
|
if (!timer_is_periodic(timer)
|
|
|| (timer->config & HPET_TN_SETVAL)) {
|
|
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
|
|
} else {
|
|
/*
|
|
* FIXME: Clamp period to reasonable min value?
|
|
* Clamp period to reasonable max value
|
|
*/
|
|
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
|
|
timer->period =
|
|
(timer->period & 0xffffffffULL) | new_val << 32;
|
|
}
|
|
timer->config &= ~HPET_TN_SETVAL;
|
|
if (hpet_enabled(s)) {
|
|
hpet_set_timer(timer);
|
|
}
|
|
break;
|
|
case HPET_TN_ROUTE:
|
|
timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
|
|
break;
|
|
case HPET_TN_ROUTE + 4:
|
|
timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
|
|
break;
|
|
default:
|
|
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
|
break;
|
|
}
|
|
return;
|
|
} else {
|
|
switch (index) {
|
|
case HPET_ID:
|
|
return;
|
|
case HPET_CFG:
|
|
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
|
|
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
|
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
|
/* Enable main counter and interrupt generation. */
|
|
s->hpet_offset =
|
|
ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
|
|
for (i = 0; i < s->num_timers; i++) {
|
|
if ((&s->timer[i])->cmp != ~0ULL) {
|
|
hpet_set_timer(&s->timer[i]);
|
|
}
|
|
}
|
|
} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
|
/* Halt main counter and disable interrupt generation. */
|
|
s->hpet_counter = hpet_get_ticks(s);
|
|
for (i = 0; i < s->num_timers; i++) {
|
|
hpet_del_timer(&s->timer[i]);
|
|
}
|
|
}
|
|
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
|
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
|
hpet_pit_disable();
|
|
qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
|
|
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
|
hpet_pit_enable();
|
|
qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
|
|
}
|
|
break;
|
|
case HPET_CFG + 4:
|
|
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
|
|
break;
|
|
case HPET_STATUS:
|
|
val = new_val & s->isr;
|
|
for (i = 0; i < s->num_timers; i++) {
|
|
if (val & (1 << i)) {
|
|
update_irq(&s->timer[i], 0);
|
|
}
|
|
}
|
|
break;
|
|
case HPET_COUNTER:
|
|
if (hpet_enabled(s)) {
|
|
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
|
}
|
|
s->hpet_counter =
|
|
(s->hpet_counter & 0xffffffff00000000ULL) | value;
|
|
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
|
|
value, s->hpet_counter);
|
|
break;
|
|
case HPET_COUNTER + 4:
|
|
if (hpet_enabled(s)) {
|
|
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
|
}
|
|
s->hpet_counter =
|
|
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
|
|
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
|
|
value, s->hpet_counter);
|
|
break;
|
|
default:
|
|
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static CPUReadMemoryFunc * const hpet_ram_read[] = {
|
|
#ifdef HPET_DEBUG
|
|
hpet_ram_readb,
|
|
hpet_ram_readw,
|
|
#else
|
|
NULL,
|
|
NULL,
|
|
#endif
|
|
hpet_ram_readl,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const hpet_ram_write[] = {
|
|
#ifdef HPET_DEBUG
|
|
hpet_ram_writeb,
|
|
hpet_ram_writew,
|
|
#else
|
|
NULL,
|
|
NULL,
|
|
#endif
|
|
hpet_ram_writel,
|
|
};
|
|
|
|
static void hpet_reset(DeviceState *d)
|
|
{
|
|
HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
|
|
int i;
|
|
static int count = 0;
|
|
|
|
for (i = 0; i < s->num_timers; i++) {
|
|
HPETTimer *timer = &s->timer[i];
|
|
|
|
hpet_del_timer(timer);
|
|
timer->cmp = ~0ULL;
|
|
timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
|
|
if (s->flags & (1 << HPET_MSI_SUPPORT)) {
|
|
timer->config |= HPET_TN_FSB_CAP;
|
|
}
|
|
/* advertise availability of ioapic inti2 */
|
|
timer->config |= 0x00000004ULL << 32;
|
|
timer->period = 0ULL;
|
|
timer->wrap_flag = 0;
|
|
}
|
|
|
|
s->hpet_counter = 0ULL;
|
|
s->hpet_offset = 0ULL;
|
|
s->config = 0ULL;
|
|
if (count > 0) {
|
|
/* we don't enable pit when hpet_reset is first called (by hpet_init)
|
|
* because hpet is taking over for pit here. On subsequent invocations,
|
|
* hpet_reset is called due to system reset. At this point control must
|
|
* be returned to pit until SW reenables hpet.
|
|
*/
|
|
hpet_pit_enable();
|
|
}
|
|
hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
|
|
hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
|
|
count = 1;
|
|
}
|
|
|
|
static void hpet_handle_rtc_irq(void *opaque, int n, int level)
|
|
{
|
|
HPETState *s = FROM_SYSBUS(HPETState, opaque);
|
|
|
|
s->rtc_irq_level = level;
|
|
if (!hpet_in_legacy_mode(s)) {
|
|
qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
|
|
}
|
|
}
|
|
|
|
static int hpet_init(SysBusDevice *dev)
|
|
{
|
|
HPETState *s = FROM_SYSBUS(HPETState, dev);
|
|
int i, iomemtype;
|
|
HPETTimer *timer;
|
|
|
|
if (hpet_cfg.count == UINT8_MAX) {
|
|
/* first instance */
|
|
hpet_cfg.count = 0;
|
|
}
|
|
|
|
if (hpet_cfg.count == 8) {
|
|
fprintf(stderr, "Only 8 instances of HPET is allowed\n");
|
|
return -1;
|
|
}
|
|
|
|
s->hpet_id = hpet_cfg.count++;
|
|
|
|
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
|
|
sysbus_init_irq(dev, &s->irqs[i]);
|
|
}
|
|
|
|
if (s->num_timers < HPET_MIN_TIMERS) {
|
|
s->num_timers = HPET_MIN_TIMERS;
|
|
} else if (s->num_timers > HPET_MAX_TIMERS) {
|
|
s->num_timers = HPET_MAX_TIMERS;
|
|
}
|
|
for (i = 0; i < HPET_MAX_TIMERS; i++) {
|
|
timer = &s->timer[i];
|
|
timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
|
|
timer->tn = i;
|
|
timer->state = s;
|
|
}
|
|
|
|
/* 64-bit main counter; LegacyReplacementRoute. */
|
|
s->capability = 0x8086a001ULL;
|
|
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
|
|
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
|
|
|
qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
|
|
|
|
/* HPET Area */
|
|
iomemtype = cpu_register_io_memory(hpet_ram_read,
|
|
hpet_ram_write, s,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
sysbus_init_mmio(dev, 0x400, iomemtype);
|
|
return 0;
|
|
}
|
|
|
|
static SysBusDeviceInfo hpet_device_info = {
|
|
.qdev.name = "hpet",
|
|
.qdev.size = sizeof(HPETState),
|
|
.qdev.no_user = 1,
|
|
.qdev.vmsd = &vmstate_hpet,
|
|
.qdev.reset = hpet_reset,
|
|
.init = hpet_init,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
|
|
DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
},
|
|
};
|
|
|
|
static void hpet_register_device(void)
|
|
{
|
|
sysbus_register_withprop(&hpet_device_info);
|
|
}
|
|
|
|
device_init(hpet_register_device)
|