mirror of https://gitee.com/openkylin/qemu.git
217 lines
4.9 KiB
C
217 lines
4.9 KiB
C
/*
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* Software MMU support
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*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* MMU mode suffixes are defined in target cpu.h.
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*/
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/* XXX: find something cleaner.
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* Furthermore, this is false for 64 bits targets
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*/
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#define ldul_user ldl_user
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#define ldul_kernel ldl_kernel
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#define ldul_hypv ldl_hypv
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#define ldul_executive ldl_executive
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#define ldul_supervisor ldl_supervisor
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/* The memory helpers for tcg-generated code need tcg_target_long etc. */
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#include "tcg.h"
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#define ACCESS_TYPE 0
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#define MEMSUFFIX MMU_MODE0_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#define ACCESS_TYPE 1
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#define MEMSUFFIX MMU_MODE1_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#if (NB_MMU_MODES >= 3)
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#define ACCESS_TYPE 2
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#define MEMSUFFIX MMU_MODE2_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 3) */
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#if (NB_MMU_MODES >= 4)
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#define ACCESS_TYPE 3
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#define MEMSUFFIX MMU_MODE3_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 4) */
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#if (NB_MMU_MODES >= 5)
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#define ACCESS_TYPE 4
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#define MEMSUFFIX MMU_MODE4_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 5) */
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#if (NB_MMU_MODES >= 6)
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#define ACCESS_TYPE 5
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#define MEMSUFFIX MMU_MODE5_SUFFIX
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 6) */
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#if (NB_MMU_MODES > 6)
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#error "NB_MMU_MODES > 6 is not supported for now"
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#endif /* (NB_MMU_MODES > 6) */
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/* these access are slower, they must be as rare as possible */
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#define ACCESS_TYPE (NB_MMU_MODES)
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#define MEMSUFFIX _data
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#define DATA_SIZE 1
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 2
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 4
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#include "exec/softmmu_header.h"
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#define DATA_SIZE 8
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#include "exec/softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#define ldub(p) ldub_data(p)
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#define ldsb(p) ldsb_data(p)
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#define lduw(p) lduw_data(p)
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#define ldsw(p) ldsw_data(p)
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#define ldl(p) ldl_data(p)
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#define ldq(p) ldq_data(p)
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#define stb(p, v) stb_data(p, v)
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#define stw(p, v) stw_data(p, v)
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#define stl(p, v) stl_data(p, v)
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#define stq(p, v) stq_data(p, v)
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If the TLB contains a host virtual address suitable for direct RAM
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* access, then return it. Otherwise (TLB miss, TLB entry is for an
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* I/O access, etc) return NULL.
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*
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* This is the equivalent of the initial fast-path code used by
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* TCG backends for guest load and store accesses.
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*/
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static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr,
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int access_type, int mmu_idx)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
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target_ulong tlb_addr;
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uintptr_t haddr;
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switch (access_type) {
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case 0:
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tlb_addr = tlbentry->addr_read;
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break;
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case 1:
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tlb_addr = tlbentry->addr_write;
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break;
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case 2:
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tlb_addr = tlbentry->addr_code;
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break;
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default:
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g_assert_not_reached();
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}
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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/* TLB entry is for a different page */
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return NULL;
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}
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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return NULL;
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}
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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return (void *)haddr;
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}
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