mirror of https://gitee.com/openkylin/qemu.git
742 lines
21 KiB
C
742 lines
21 KiB
C
/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement boot blocs with reduced size
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "hw.h"
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#include "flash.h"
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#include "qemu-timer.h"
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#include "block.h"
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//#define PFLASH_DEBUG
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, ...) \
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do { \
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printf("PFLASH: " fmt , ## __VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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struct pflash_t {
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BlockDriverState *bs;
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target_phys_addr_t base;
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uint32_t sector_len;
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uint32_t chip_len;
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int mappings;
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int width;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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int ro;
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uint8_t cmd;
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uint8_t status;
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uint16_t ident[4];
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uint16_t unlock_addr[2];
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uint8_t cfi_len;
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uint8_t cfi_table[0x52];
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QEMUTimer *timer;
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ram_addr_t off;
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int fl_mem;
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int rom_mode;
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void *storage;
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};
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static void pflash_register_memory(pflash_t *pfl, int rom_mode)
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{
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unsigned long phys_offset = pfl->fl_mem;
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int i;
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if (rom_mode)
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phys_offset |= pfl->off | IO_MEM_ROMD;
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pfl->rom_mode = rom_mode;
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for (i = 0; i < pfl->mappings; i++)
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cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
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pfl->chip_len, phys_offset);
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}
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static void pflash_timer (void *opaque)
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{
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pflash_t *pfl = opaque;
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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pflash_register_memory(pfl, 1);
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pfl->wcycle = 0;
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}
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pfl->cmd = 0;
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}
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static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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int width, int be)
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{
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target_phys_addr_t boff;
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uint32_t ret;
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uint8_t *p;
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DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
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ret = -1;
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if (pfl->rom_mode) {
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/* Lazy reset of to ROMD mode */
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if (pfl->wcycle == 0)
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pflash_register_memory(pfl, 1);
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}
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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case 0x80:
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/* We accept reads during second unlock sequence... */
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case 0x00:
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flash_read:
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/* Flash area read */
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p = pfl->storage;
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switch (width) {
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case 1:
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ret = p[offset];
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2:
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if (be) {
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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}
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4:
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if (be) {
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16;
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ret |= p[offset + 2] << 8;
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ret |= p[offset + 3];
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} else {
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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}
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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}
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break;
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case 0x90:
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/* flash ID read */
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switch (boff) {
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case 0x00:
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case 0x01:
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ret = pfl->ident[boff & 0x01];
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break;
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case 0x02:
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ret = 0x00; /* Pretend all sectors are unprotected */
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break;
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case 0x0E:
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case 0x0F:
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if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
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goto flash_read;
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ret = pfl->ident[2 + (boff & 0x01)];
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break;
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default:
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goto flash_read;
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}
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DPRINTF("%s: ID " TARGET_FMT_pld " %x\n", __func__, boff, ret);
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break;
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case 0xA0:
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case 0x10:
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case 0x30:
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/* Status register read */
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ret = pfl->status;
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DPRINTF("%s: status %x\n", __func__, ret);
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/* Toggle bit 6 */
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pfl->status ^= 0x40;
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break;
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case 0x98:
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/* CFI query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff];
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break;
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}
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return ret;
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}
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset,
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int size)
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{
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size;
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9;
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset);
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}
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}
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static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
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uint32_t value, int width, int be)
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{
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target_phys_addr_t boff;
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uint8_t *p;
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uint8_t cmd;
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cmd = value;
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if (pfl->cmd != 0xA0 && cmd == 0xF0) {
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#if 0
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DPRINTF("%s: flash reset asked (%02x %02x)\n",
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__func__, pfl->cmd, cmd);
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#endif
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goto reset_flash;
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}
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DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
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offset, value, width, pfl->wcycle);
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offset &= pfl->chip_len - 1;
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DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
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offset, value, width);
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2)
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boff = boff >> 1;
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else if (pfl->width == 4)
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boff = boff >> 2;
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switch (pfl->wcycle) {
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case 0:
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/* Set the device in I/O access mode if required */
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if (pfl->rom_mode)
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pflash_register_memory(pfl, 0);
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/* We're in read mode */
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check_unlock0:
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if (boff == 0x55 && cmd == 0x98) {
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enter_CFI_mode:
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/* Enter CFI query mode */
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pfl->wcycle = 7;
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pfl->cmd = 0x98;
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return;
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}
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if (boff != pfl->unlock_addr[0] || cmd != 0xAA) {
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DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
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__func__, boff, cmd, pfl->unlock_addr[0]);
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goto reset_flash;
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}
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DPRINTF("%s: unlock sequence started\n", __func__);
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break;
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case 1:
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/* We started an unlock sequence */
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check_unlock1:
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if (boff != pfl->unlock_addr[1] || cmd != 0x55) {
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DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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DPRINTF("%s: unlock sequence done\n", __func__);
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break;
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case 2:
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/* We finished an unlock sequence */
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if (!pfl->bypass && boff != pfl->unlock_addr[0]) {
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DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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switch (cmd) {
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case 0x20:
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pfl->bypass = 1;
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goto do_bypass;
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case 0x80:
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case 0x90:
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case 0xA0:
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pfl->cmd = cmd;
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DPRINTF("%s: starting command %02x\n", __func__, cmd);
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break;
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default:
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DPRINTF("%s: unknown command %02x\n", __func__, cmd);
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goto reset_flash;
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}
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break;
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case 3:
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switch (pfl->cmd) {
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case 0x80:
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/* We need another unlock sequence */
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goto check_unlock0;
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case 0xA0:
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DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
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__func__, offset, value, width);
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p = pfl->storage;
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switch (width) {
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case 1:
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p[offset] &= value;
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pflash_update(pfl, offset, 1);
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break;
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case 2:
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if (be) {
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p[offset] &= value >> 8;
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p[offset + 1] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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}
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pflash_update(pfl, offset, 2);
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break;
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case 4:
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if (be) {
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p[offset] &= value >> 24;
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p[offset + 1] &= value >> 16;
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p[offset + 2] &= value >> 8;
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p[offset + 3] &= value;
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} else {
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p[offset] &= value;
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p[offset + 1] &= value >> 8;
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p[offset + 2] &= value >> 16;
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p[offset + 3] &= value >> 24;
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}
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pflash_update(pfl, offset, 4);
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break;
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}
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pfl->status = 0x00 | ~(value & 0x80);
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/* Let's pretend write is immediate */
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if (pfl->bypass)
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goto do_bypass;
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goto reset_flash;
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case 0x90:
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if (pfl->bypass && cmd == 0x00) {
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/* Unlock bypass reset */
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goto reset_flash;
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}
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/* We can enter CFI query mode from autoselect mode */
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if (boff == 0x55 && cmd == 0x98)
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goto enter_CFI_mode;
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/* No break here */
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default:
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DPRINTF("%s: invalid write for command %02x\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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case 4:
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switch (pfl->cmd) {
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case 0xA0:
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/* Ignore writes while flash data write is occuring */
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/* As we suppose write is immediate, this should never happen */
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return;
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case 0x80:
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goto check_unlock1;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid command state %02x (wc 4)\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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break;
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case 5:
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switch (cmd) {
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case 0x10:
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if (boff != pfl->unlock_addr[0]) {
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DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
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__func__, offset);
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goto reset_flash;
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}
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/* Chip erase */
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DPRINTF("%s: start chip erase\n", __func__);
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memset(pfl->storage, 0xFF, pfl->chip_len);
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pfl->status = 0x00;
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pflash_update(pfl, 0, pfl->chip_len);
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/* Let's wait 5 seconds before chip erase is done */
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qemu_mod_timer(pfl->timer,
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qemu_get_clock(vm_clock) + (get_ticks_per_sec() * 5));
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break;
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case 0x30:
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/* Sector erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
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offset);
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memset(p + offset, 0xFF, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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pfl->status = 0x00;
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/* Let's wait 1/2 second before sector erase is done */
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qemu_mod_timer(pfl->timer,
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qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 2));
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break;
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default:
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DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
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goto reset_flash;
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}
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pfl->cmd = cmd;
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break;
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case 6:
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switch (pfl->cmd) {
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case 0x10:
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/* Ignore writes during chip erase */
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return;
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case 0x30:
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/* Ignore writes during sector erase */
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return;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid command state %02x (wc 6)\n",
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__func__, pfl->cmd);
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goto reset_flash;
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}
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break;
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case 7: /* Special value for CFI queries */
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DPRINTF("%s: invalid write in CFI query mode\n", __func__);
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goto reset_flash;
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default:
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/* Should never happen */
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DPRINTF("%s: invalid write state (wc 7)\n", __func__);
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goto reset_flash;
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}
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pfl->wcycle++;
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|
|
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return;
|
|
|
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/* Reset flash */
|
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reset_flash:
|
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pfl->bypass = 0;
|
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pfl->wcycle = 0;
|
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pfl->cmd = 0;
|
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return;
|
|
|
|
do_bypass:
|
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pfl->wcycle = 2;
|
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pfl->cmd = 0;
|
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return;
|
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}
|
|
|
|
|
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static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
|
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{
|
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return pflash_read(opaque, addr, 1, 1);
|
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}
|
|
|
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static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
|
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{
|
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return pflash_read(opaque, addr, 1, 0);
|
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}
|
|
|
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static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
|
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{
|
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pflash_t *pfl = opaque;
|
|
|
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return pflash_read(pfl, addr, 2, 1);
|
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}
|
|
|
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static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
|
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{
|
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pflash_t *pfl = opaque;
|
|
|
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return pflash_read(pfl, addr, 2, 0);
|
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}
|
|
|
|
static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
|
|
{
|
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pflash_t *pfl = opaque;
|
|
|
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return pflash_read(pfl, addr, 4, 1);
|
|
}
|
|
|
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static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
|
|
{
|
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pflash_t *pfl = opaque;
|
|
|
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return pflash_read(pfl, addr, 4, 0);
|
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}
|
|
|
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static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
|
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uint32_t value)
|
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{
|
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pflash_write(opaque, addr, value, 1, 1);
|
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}
|
|
|
|
static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
|
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uint32_t value)
|
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{
|
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pflash_write(opaque, addr, value, 1, 0);
|
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}
|
|
|
|
static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
pflash_t *pfl = opaque;
|
|
|
|
pflash_write(pfl, addr, value, 2, 1);
|
|
}
|
|
|
|
static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
pflash_t *pfl = opaque;
|
|
|
|
pflash_write(pfl, addr, value, 2, 0);
|
|
}
|
|
|
|
static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
pflash_t *pfl = opaque;
|
|
|
|
pflash_write(pfl, addr, value, 4, 1);
|
|
}
|
|
|
|
static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
|
|
uint32_t value)
|
|
{
|
|
pflash_t *pfl = opaque;
|
|
|
|
pflash_write(pfl, addr, value, 4, 0);
|
|
}
|
|
|
|
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
|
|
&pflash_writeb_be,
|
|
&pflash_writew_be,
|
|
&pflash_writel_be,
|
|
};
|
|
|
|
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
|
|
&pflash_readb_be,
|
|
&pflash_readw_be,
|
|
&pflash_readl_be,
|
|
};
|
|
|
|
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
|
|
&pflash_writeb_le,
|
|
&pflash_writew_le,
|
|
&pflash_writel_le,
|
|
};
|
|
|
|
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
|
|
&pflash_readb_le,
|
|
&pflash_readw_le,
|
|
&pflash_readl_le,
|
|
};
|
|
|
|
/* Count trailing zeroes of a 32 bits quantity */
|
|
static int ctz32 (uint32_t n)
|
|
{
|
|
int ret;
|
|
|
|
ret = 0;
|
|
if (!(n & 0xFFFF)) {
|
|
ret += 16;
|
|
n = n >> 16;
|
|
}
|
|
if (!(n & 0xFF)) {
|
|
ret += 8;
|
|
n = n >> 8;
|
|
}
|
|
if (!(n & 0xF)) {
|
|
ret += 4;
|
|
n = n >> 4;
|
|
}
|
|
if (!(n & 0x3)) {
|
|
ret += 2;
|
|
n = n >> 2;
|
|
}
|
|
if (!(n & 0x1)) {
|
|
ret++;
|
|
#if 0 /* This is not necessary as n is never 0 */
|
|
n = n >> 1;
|
|
#endif
|
|
}
|
|
#if 0 /* This is not necessary as n is never 0 */
|
|
if (!n)
|
|
ret++;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
|
|
BlockDriverState *bs, uint32_t sector_len,
|
|
int nb_blocs, int nb_mappings, int width,
|
|
uint16_t id0, uint16_t id1,
|
|
uint16_t id2, uint16_t id3,
|
|
uint16_t unlock_addr0, uint16_t unlock_addr1,
|
|
int be)
|
|
{
|
|
pflash_t *pfl;
|
|
int32_t chip_len;
|
|
int ret;
|
|
|
|
chip_len = sector_len * nb_blocs;
|
|
/* XXX: to be fixed */
|
|
#if 0
|
|
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
|
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
|
return NULL;
|
|
#endif
|
|
pfl = qemu_mallocz(sizeof(pflash_t));
|
|
/* FIXME: Allocate ram ourselves. */
|
|
pfl->storage = qemu_get_ram_ptr(off);
|
|
if (be) {
|
|
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
|
|
pflash_write_ops_be,
|
|
pfl);
|
|
} else {
|
|
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
|
|
pflash_write_ops_le,
|
|
pfl);
|
|
}
|
|
pfl->off = off;
|
|
pfl->base = base;
|
|
pfl->chip_len = chip_len;
|
|
pfl->mappings = nb_mappings;
|
|
pflash_register_memory(pfl, 1);
|
|
pfl->bs = bs;
|
|
if (pfl->bs) {
|
|
/* read the initial flash content */
|
|
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
|
|
if (ret < 0) {
|
|
cpu_unregister_io_memory(pfl->fl_mem);
|
|
qemu_free(pfl);
|
|
return NULL;
|
|
}
|
|
}
|
|
#if 0 /* XXX: there should be a bit to set up read-only,
|
|
* the same way the hardware does (with WP pin).
|
|
*/
|
|
pfl->ro = 1;
|
|
#else
|
|
pfl->ro = 0;
|
|
#endif
|
|
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
|
|
pfl->sector_len = sector_len;
|
|
pfl->width = width;
|
|
pfl->wcycle = 0;
|
|
pfl->cmd = 0;
|
|
pfl->status = 0;
|
|
pfl->ident[0] = id0;
|
|
pfl->ident[1] = id1;
|
|
pfl->ident[2] = id2;
|
|
pfl->ident[3] = id3;
|
|
pfl->unlock_addr[0] = unlock_addr0;
|
|
pfl->unlock_addr[1] = unlock_addr1;
|
|
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
|
pfl->cfi_len = 0x52;
|
|
/* Standard "QRY" string */
|
|
pfl->cfi_table[0x10] = 'Q';
|
|
pfl->cfi_table[0x11] = 'R';
|
|
pfl->cfi_table[0x12] = 'Y';
|
|
/* Command set (AMD/Fujitsu) */
|
|
pfl->cfi_table[0x13] = 0x02;
|
|
pfl->cfi_table[0x14] = 0x00;
|
|
/* Primary extended table address */
|
|
pfl->cfi_table[0x15] = 0x31;
|
|
pfl->cfi_table[0x16] = 0x00;
|
|
/* Alternate command set (none) */
|
|
pfl->cfi_table[0x17] = 0x00;
|
|
pfl->cfi_table[0x18] = 0x00;
|
|
/* Alternate extended table (none) */
|
|
pfl->cfi_table[0x19] = 0x00;
|
|
pfl->cfi_table[0x1A] = 0x00;
|
|
/* Vcc min */
|
|
pfl->cfi_table[0x1B] = 0x27;
|
|
/* Vcc max */
|
|
pfl->cfi_table[0x1C] = 0x36;
|
|
/* Vpp min (no Vpp pin) */
|
|
pfl->cfi_table[0x1D] = 0x00;
|
|
/* Vpp max (no Vpp pin) */
|
|
pfl->cfi_table[0x1E] = 0x00;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x1F] = 0x07;
|
|
/* Timeout for min size buffer write (NA) */
|
|
pfl->cfi_table[0x20] = 0x00;
|
|
/* Typical timeout for block erase (512 ms) */
|
|
pfl->cfi_table[0x21] = 0x09;
|
|
/* Typical timeout for full chip erase (4096 ms) */
|
|
pfl->cfi_table[0x22] = 0x0C;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x23] = 0x01;
|
|
/* Max timeout for buffer write (NA) */
|
|
pfl->cfi_table[0x24] = 0x00;
|
|
/* Max timeout for block erase */
|
|
pfl->cfi_table[0x25] = 0x0A;
|
|
/* Max timeout for chip erase */
|
|
pfl->cfi_table[0x26] = 0x0D;
|
|
/* Device size */
|
|
pfl->cfi_table[0x27] = ctz32(chip_len);
|
|
/* Flash device interface (8 & 16 bits) */
|
|
pfl->cfi_table[0x28] = 0x02;
|
|
pfl->cfi_table[0x29] = 0x00;
|
|
/* Max number of bytes in multi-bytes write */
|
|
/* XXX: disable buffered write as it's not supported */
|
|
// pfl->cfi_table[0x2A] = 0x05;
|
|
pfl->cfi_table[0x2A] = 0x00;
|
|
pfl->cfi_table[0x2B] = 0x00;
|
|
/* Number of erase block regions (uniform) */
|
|
pfl->cfi_table[0x2C] = 0x01;
|
|
/* Erase block region 1 */
|
|
pfl->cfi_table[0x2D] = nb_blocs - 1;
|
|
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
|
|
pfl->cfi_table[0x2F] = sector_len >> 8;
|
|
pfl->cfi_table[0x30] = sector_len >> 16;
|
|
|
|
/* Extended */
|
|
pfl->cfi_table[0x31] = 'P';
|
|
pfl->cfi_table[0x32] = 'R';
|
|
pfl->cfi_table[0x33] = 'I';
|
|
|
|
pfl->cfi_table[0x34] = '1';
|
|
pfl->cfi_table[0x35] = '0';
|
|
|
|
pfl->cfi_table[0x36] = 0x00;
|
|
pfl->cfi_table[0x37] = 0x00;
|
|
pfl->cfi_table[0x38] = 0x00;
|
|
pfl->cfi_table[0x39] = 0x00;
|
|
|
|
pfl->cfi_table[0x3a] = 0x00;
|
|
|
|
pfl->cfi_table[0x3b] = 0x00;
|
|
pfl->cfi_table[0x3c] = 0x00;
|
|
|
|
return pfl;
|
|
}
|