Paul Burton 62be393423 hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller ... Add support for emulating the Xilinx AXI Root Port Bridge for PCI Express as described by Xilinx' PG055 document. This is a PCIe controller that can be used with certain series of Xilinx FPGAs, and is used on the MIPS Boston board which will make use of this code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [yongbok.kim@imgtec.com: removed returning on !level, updated IRQ connection with GPIO logic, moved xilinx_pcie_init() to boston.c replaced stw_le_p() with pci_set_word() and other cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>		2017-02-21 23:49:29 +00:00
..
apb.h	Clean up header guards that don't match their file name	2016-07-12 16:19:16 +02:00
gpex.h	pci: Add generic PCIe host bridge	2015-02-13 05:46:07 +00:00
pam.h	hw/i386: remove smram_update	2015-06-05 17:36:39 +02:00
ppce500.h	Clean up header guards that don't match their file name	2016-07-12 16:19:16 +02:00
q35.h	include: Fix typos found by codespell	2017-01-24 23:26:52 +03:00
spapr.h	spapr: Fix 2.7<->2.8 migration of PCI host bridge	2016-11-23 12:00:48 +11:00
xilinx-pcie.h	hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller	2017-02-21 23:49:29 +00:00