mirror of https://gitee.com/openkylin/qemu.git
132 lines
4.0 KiB
C
132 lines
4.0 KiB
C
/*
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* QTest testcase for the CMSDK APB watchdog device
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*
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* Copyright (c) 2021 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "libqtest-single.h"
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/*
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* lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
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* which is 80ns per tick.
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*/
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#define WDOG_BASE 0x40000000
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#define WDOGLOAD 0
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#define WDOGVALUE 4
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#define WDOGCONTROL 8
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#define WDOGINTCLR 0xc
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#define WDOGRIS 0x10
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#define WDOGMIS 0x14
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#define WDOGLOCK 0xc00
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#define SSYS_BASE 0x400fe000
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#define RCC 0x60
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#define SYSDIV_SHIFT 23
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#define SYSDIV_LENGTH 4
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static void test_watchdog(void)
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{
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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writel(WDOG_BASE + WDOGCONTROL, 1);
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writel(WDOG_BASE + WDOGLOAD, 1000);
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/* Step to just past the 500th tick */
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clock_step(500 * 80 + 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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/* Just past the 1000th tick: timer should have fired */
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clock_step(500 * 80);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
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/* VALUE reloads at following tick */
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clock_step(80);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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/* Writing any value to WDOGINTCLR clears the interrupt and reloads */
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clock_step(500 * 80);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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writel(WDOG_BASE + WDOGINTCLR, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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}
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static void test_clock_change(void)
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{
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uint32_t rcc;
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/*
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* Test that writing to the stellaris board's RCC register to
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* change the system clock frequency causes the watchdog
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* to change the speed it counts at.
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*/
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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writel(WDOG_BASE + WDOGCONTROL, 1);
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writel(WDOG_BASE + WDOGLOAD, 1000);
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/* Step to just past the 500th tick */
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clock_step(80 * 500 + 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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/* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
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rcc = readl(SSYS_BASE + RCC);
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g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
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rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
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writel(SSYS_BASE + RCC, rcc);
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/* Just past the 1000th tick: timer should have fired */
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clock_step(40 * 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
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/* VALUE reloads at following tick */
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clock_step(41);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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/* Writing any value to WDOGINTCLR clears the interrupt and reloads */
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clock_step(40 * 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
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writel(WDOG_BASE + WDOGINTCLR, 0);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
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g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
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}
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int main(int argc, char **argv)
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{
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int r;
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g_test_init(&argc, &argv, NULL);
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qtest_start("-machine lm3s811evb");
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qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
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qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
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test_clock_change);
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r = g_test_run();
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qtest_end();
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return r;
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}
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