qemu/target-sparc
Igor V. Kovalenko 664a65b0db sparc64: flush translations on mmu context change
- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
  using value of DMMU primary and secondary context registers, so we need to
  flush softmmu translations when context registers are changed

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22 12:52:38 +00:00
..
TODO Remove unnecessary trailing newlines 2008-12-13 09:32:43 +00:00
cpu.h sparc64: fix mmu context at trap levels above zero 2010-05-22 12:51:48 +00:00
exec.h sparc: move DT and QT defines to op_helper.c 2010-05-16 08:33:02 +00:00
helper.c sparc64: fix mmu context at trap levels above zero 2010-05-22 12:51:48 +00:00
helper.h target-sparc: Inline some generation of carry for ADDX/SUBX. 2010-05-20 19:58:28 +00:00
machine.c sparc: Fix lazy flag calculation on interrupts, refactor 2010-05-09 20:19:04 +00:00
op_helper.c sparc64: flush translations on mmu context change 2010-05-22 12:52:38 +00:00
translate.c sparc64: fix mmu context at trap levels above zero 2010-05-22 12:51:48 +00:00