Peter Maydell dda3ec490c target-arm: Fix VRECPS edge cases handling ... Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-03-22 07:59:06 +01:00
..
cpu.h	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
exec.h	inline cpu_halted into sole caller	2011-03-13 14:44:21 +00:00
helper.c	target-arm: Fix VRECPS edge cases handling	2011-03-22 07:59:06 +01:00
helpers.h	target-arm: Move Neon VZIP to helper functions	2011-02-20 17:31:53 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
neon_helper.c	target-arm: Fix unsigned VQRSHL by large shift counts	2011-02-20 17:43:01 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
translate.c	target-arm: Fix TCG temporary leaks for scalar VMULL	2011-03-22 07:56:30 +01:00