mirror of https://gitee.com/openkylin/qemu.git
301 lines
9.8 KiB
C
301 lines
9.8 KiB
C
// SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
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/* Copyright 2013-2019 IBM Corp. */
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#ifndef __XSCOM_H
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#define __XSCOM_H
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#include <stdint.h>
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#include <processor.h>
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#include <cpu.h>
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/*
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* SCOM "partID" definitions:
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*
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* All Ids are 32-bits long, top nibble is reserved for the
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* 'type' field:
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* 0x0 = Processor Chip
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* 0x8 = Memory Buffer (Centaur) Chip
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* 0x4 = EX/Core Chiplet
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*
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* Processor Chip = Logical Fabric Id = PIR>>7
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* 0b0000.0000.0000.0000.0000.0000.00NN.NCCC
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* N=Node, C=Chip
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* Centaur Chip = Associated Processor Chip with memory channel
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* appended and flag set
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* 0b1000.0000.0000.0000.0000.00NN.NCCC.MMMM
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* N=Node, C=Chip, M=Memory Channel
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* Processor EX/Core chiplet = PIR >> 3 with flag set.
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* On P8:
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* 0b0100.0000.0000.0000.0000.00NN.NCCC.PPPP
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* On P9:
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* 0b0100.0000.0000.0000.0000.0NNN.CCCP.PPPP
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* N=Node, C=Chip, P=Processor core
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*/
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/*
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* SCOM Address definition extracted from HWPs for documentation
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* purposes
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*
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* "Normal" (legacy) format
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*
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* 111111 11112222 22222233 33333333 44444444 44555555 55556666
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* 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123
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* -------- -------- -------- -------- -------- -------- -------- --------
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* 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL
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* || | |
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* || | `-> Local Address*
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* || |
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* || `-> Port
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* ||
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* |`-> Chiplet ID**
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* |
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* `-> Multicast bit
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*
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* * Local address is composed of "00" + 4-bit ring + 10-bit ID
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* The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id
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*
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* ** Chiplet ID turns into multicast operation type and group number
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* if the multicast bit is set
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*
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* "Indirect" format
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*
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*
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* 111111 11112222 22222233 33333333 44444444 44555555 55556666
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* 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123
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* -------- -------- -------- -------- -------- -------- -------- --------
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* 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL
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* | | | || | |
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* | | | || | `-> Local Address*
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* | | | || |
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* | | | || `-> Port
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* | | | ||
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* | | | |`-> Chiplet ID**
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* | | | |
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* | | | `-> Multicast bit
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* | | |
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* | | `-> Lane ID
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* | |
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* | `-> RX or TX Group ID
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* |
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* `-> Indirect Register Address
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*
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* * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111"
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*
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* ** Chiplet ID turns into multicast operation type and group number
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* if the multicast bit is set
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*/
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/*
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* Generate a local address from a given ring/satellite/offset
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* combination:
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*
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* Ring Satellite offset
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* +---------+---------+-------------+
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* | 4 | 4 | 6 |
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* +---------+---------+-------------+
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*/
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#define XSCOM_SAT(_r, _s, _o) \
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(((_r) << 10) | ((_s) << 6) | (_o))
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/*
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* Additional useful definitions for P8
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*/
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#define P8_EX_PCB_SLAVE_BASE 0x100F0000
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#define XSCOM_ADDR_P8_EX_SLAVE(core, offset) \
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(P8_EX_PCB_SLAVE_BASE | (((core) & 0xF) << 24) | ((offset) & 0xFFFF))
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#define XSCOM_ADDR_P8_EX(core, addr) \
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((((core) & 0xF) << 24) | (addr))
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/*
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* Additional useful definitions for P9
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*
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* Note: In all of these, the core numbering is the
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* *normal* (small) core number.
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*/
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/*
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* An EQ is a quad. The Pervasive spec also uses the term "EP"
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* to refer to an EQ and it's two child EX chiplets, but
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* nothing else does
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*/
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#define XSCOM_ADDR_P9_EQ(core, addr) \
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(((((core) & 0x1c) + 0x40) << 22) | (addr))
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#define XSCOM_ADDR_P9_EQ_SLAVE(core, addr) \
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XSCOM_ADDR_P9_EQ(core, (addr) | 0xf0000)
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/* An EX is a pair of cores. They are accessed via their corresponding EQs
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* with bit 0x400 indicating which of the 2 EX to address
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*/
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#define XSCOM_ADDR_P9_EX(core, addr) \
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(XSCOM_ADDR_P9_EQ(core, addr | (((core) & 2) << 9)))
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/* An EC is an individual core and has its own XSCOM addressing */
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#define XSCOM_ADDR_P9_EC(core, addr) \
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(((((core) & 0x1F) + 0x20) << 24) | (addr))
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#define XSCOM_ADDR_P9_EC_SLAVE(core, addr) \
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XSCOM_ADDR_P9_EC(core, (addr) | 0xf0000)
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/*
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* Additional useful definitions for P10
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*/
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/*
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* POWER10 pervasive structure
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* Chip has 8 EQ chiplets (aka super-chiplets), and other nest chiplets.
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* Each EQ contains 4 EX regions.
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* Each EX contains an ECL2, L3, MMA.
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* Each ECL2 contains an EC (core), L2, and NCU.
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*
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* Each EQ has a Quad Management Engine (QME), responsible for power management
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* for the cores, among other things.
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*
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* POWER10 XSCOM address format:
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*
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* | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|16-31|
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* MC=0 |WR|MC|SLAVE ADDR |PIB MASTER |PORT NUMBER|LOCAL|
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* MC=1 |WR|MC|MC TYPE |MC GROUP|PIB MASTER |PORT NUMBER|LOCAL|
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*
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* * Port is also known as PSCOM endpoint.
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*
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* WR is set by the xscom access functions (XSCOM_DATA_IND_READ bit)
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* MC is always 0 (skiboot does not use multicast scoms).
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*
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* For unicast:
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* EQ0-7 is addressed from 0x20 to 0x27 in the top 8 bits.
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* L3 is on port 1
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* NCU is on port 1
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* ECL2 (core+L2) is on port 2 (XXX P10 scoms html doc suggests port 1?)
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* QME is on port E.
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*
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* EQ chiplets (aka super chiplet) local address format:
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*
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* | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|
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* |C0|C1|C2|C3|RING ID |SAT ID |REGISTER ID |
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*
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* EX0-4 are selected with one-hot encoding (C0-3)
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*
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* QME per-core register access address format:
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* | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|
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* |C0|C1|C2|C3| 1| 0| 0| 0|PER-CORE REGISTER ID |
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*
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* NCU - ring 6 (port 1)
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* L3 - ring 3 (port 1) (XXX P10 scoms html doc suggests ring 6)
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* L2 - ring 0 (port 2) (XXX P10 scoms html doc suggests ring 4)
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* EC (PC unit) - rings 2-5 (port 2)
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*
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* Other chiplets:
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*
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* | 0| 1| 2| 3| 4| 5| 6| 7| 8| 9|10|11|12|13|14|15|
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* | 1|RING ID |SAT ID |REGISTER ID |
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*/
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#define P10_CORE_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
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#define P10_CORE_PROC(core) ((core) & 0x3)
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#define XSCOM_P10_EQ(chiplet) ((chiplet) << 24)
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#define XSCOM_P10_QME(chiplet) \
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(XSCOM_P10_EQ(chiplet) | (0xE << 16))
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#define XSCOM_P10_QME_CORE(chiplet, proc) \
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(XSCOM_P10_QME(chiplet) | ((1 << (3 - proc)) << 12))
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#define XSCOM_P10_EC(chiplet, proc) \
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(XSCOM_P10_EQ(chiplet) | (0x2 << 16) | ((1 << (3 - proc)) << 12))
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#define XSCOM_P10_NCU(chiplet, proc) \
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(XSCOM_P10_EQ(chiplet) | (0x1 << 16) | ((1 << (3 - proc)) << 12))
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#define XSCOM_ADDR_P10_EQ(core, addr) \
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(XSCOM_P10_EQ(P10_CORE_EQ_CHIPLET(core)) | (addr))
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#define XSCOM_ADDR_P10_QME(core, addr) \
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(XSCOM_P10_QME(P10_CORE_EQ_CHIPLET(core)) | (addr))
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#define XSCOM_ADDR_P10_QME_CORE(core, addr) \
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(XSCOM_P10_QME_CORE(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr))
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#define XSCOM_ADDR_P10_EC(core, addr) \
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(XSCOM_P10_EC(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr))
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#define XSCOM_ADDR_P10_NCU(core, addr) \
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(XSCOM_P10_NCU(P10_CORE_EQ_CHIPLET(core), P10_CORE_PROC(core)) | (addr))
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/* Definitions relating to indirect XSCOMs shared with centaur */
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#define XSCOM_ADDR_IND_FLAG PPC_BIT(0)
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#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(12,31)
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#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48,63)
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#define XSCOM_DATA_IND_READ PPC_BIT(0)
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#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32)
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#define XSCOM_DATA_IND_ERR PPC_BITMASK(33,35)
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#define XSCOM_DATA_IND_DATA PPC_BITMASK(48,63)
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#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12,63)
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/* HB folks say: try 10 time for now */
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#define XSCOM_IND_MAX_RETRIES 10
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/* Max number of retries when XSCOM remains busy */
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#define XSCOM_BUSY_MAX_RETRIES 3000
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/* Max number of retries for xscom clearing recovery. */
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#define XSCOM_CLEAR_MAX_RETRIES 10
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/* Retry count after which to reset XSCOM, if still busy */
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#define XSCOM_BUSY_RESET_THRESHOLD 1000
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/*
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* Error handling:
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*
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* Error codes TBD, 0 = success
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*/
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/* Use only in select places where multiple SCOMs are time/latency sensitive */
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extern void _xscom_lock(void);
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extern int _xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val, bool take_lock);
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extern int _xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val, bool take_lock);
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extern void _xscom_unlock(void);
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/* Targeted SCOM access */
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static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val)
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{
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return _xscom_read(partid, pcb_addr, val, true);
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}
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static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) {
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return _xscom_write(partid, pcb_addr, val, true);
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}
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extern int xscom_write_mask(uint32_t partid, uint64_t pcb_addr, uint64_t val, uint64_t mask);
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/* This chip SCOM access */
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extern int xscom_readme(uint64_t pcb_addr, uint64_t *val);
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extern int xscom_writeme(uint64_t pcb_addr, uint64_t val);
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extern void xscom_init(void);
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/* Mark XSCOM lock as being in console path */
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extern void xscom_used_by_console(void);
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/* Returns true if XSCOM can be used. Typically this returns false if
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* the current CPU holds the XSCOM lock (to avoid re-entrancy from error path).
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*/
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extern bool xscom_ok(void);
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extern int64_t xscom_read_cfam_chipid(uint32_t partid, uint32_t *chip_id);
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extern int64_t xscom_trigger_xstop(void);
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struct scom_controller {
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uint32_t part_id;
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void *private;
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int64_t (*read)(struct scom_controller *, uint32_t chip, uint64_t reg, uint64_t *val);
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int64_t (*write)(struct scom_controller *, uint32_t chip, uint64_t reg, uint64_t val);
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struct list_node link;
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};
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int64_t scom_register(struct scom_controller *new);
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#endif /* __XSCOM_H */
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