mirror of https://gitee.com/openkylin/qemu.git
236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
/*
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* QEMU RS/6000 memory controller
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*
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* Copyright (c) 2017 Hervé Poussineau
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) version 3 or any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/isa/isa.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "trace.h"
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#define TYPE_RS6000MC "rs6000-mc"
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#define RS6000MC_DEVICE(obj) \
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OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
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typedef struct RS6000MCState {
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ISADevice parent_obj;
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/* see US patent 5,684,979 for details (expired 2001-11-04) */
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uint32_t ram_size;
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bool autoconfigure;
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MemoryRegion simm[6];
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unsigned int simm_size[6];
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uint32_t end_address[8];
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uint8_t port0820_index;
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PortioList portio;
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} RS6000MCState;
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/* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
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static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr)
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{
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RS6000MCState *s = opaque;
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uint32_t val = 0;
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int socket;
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/* (1 << socket) indicates 32 MB SIMM at given socket */
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for (socket = 0; socket < 6; socket++) {
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if (s->simm_size[socket] == 32) {
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val |= (1 << socket);
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}
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}
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trace_rs6000mc_id_read(addr, val);
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return val;
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}
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/* PORT 0804 -- SIMM Presence Register (Read Only) */
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static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr)
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{
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RS6000MCState *s = opaque;
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uint32_t val = 0xff;
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int socket;
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/* (1 << socket) indicates SIMM absence at given socket */
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for (socket = 0; socket < 6; socket++) {
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if (s->simm_size[socket]) {
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val &= ~(1 << socket);
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}
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}
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s->port0820_index = 0;
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trace_rs6000mc_presence_read(addr, val);
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return val;
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}
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/* Memory Controller Size Programming Register */
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static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr)
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{
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RS6000MCState *s = opaque;
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uint32_t val = s->end_address[s->port0820_index] & 0x1f;
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s->port0820_index = (s->port0820_index + 1) & 7;
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trace_rs6000mc_size_read(addr, val);
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return val;
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}
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static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
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{
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RS6000MCState *s = opaque;
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uint8_t socket = val >> 5;
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uint32_t end_address = val & 0x1f;
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trace_rs6000mc_size_write(addr, val);
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s->end_address[socket] = end_address;
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if (socket > 0 && socket < 7) {
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if (s->simm_size[socket - 1]) {
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uint32_t size;
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uint32_t start_address = 0;
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if (socket > 1) {
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start_address = s->end_address[socket - 1];
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}
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size = end_address - start_address;
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memory_region_set_enabled(&s->simm[socket - 1], size != 0);
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memory_region_set_address(&s->simm[socket - 1],
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start_address * 8 * MiB);
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}
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}
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}
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/* Read Memory Parity Error */
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enum {
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PORT0841_NO_ERROR_DETECTED = 0x01,
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};
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static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr)
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{
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uint32_t val = PORT0841_NO_ERROR_DETECTED;
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trace_rs6000mc_parity_read(addr, val);
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return val;
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}
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static const MemoryRegionPortio rs6000mc_port_list[] = {
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{ 0x803, 1, 1, .read = rs6000mc_port0803_read },
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{ 0x804, 1, 1, .read = rs6000mc_port0804_read },
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{ 0x820, 1, 1, .read = rs6000mc_port0820_read,
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.write = rs6000mc_port0820_write, },
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{ 0x841, 1, 1, .read = rs6000mc_port0841_read },
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PORTIO_END_OF_LIST()
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};
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static void rs6000mc_realize(DeviceState *dev, Error **errp)
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{
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RS6000MCState *s = RS6000MC_DEVICE(dev);
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int socket = 0;
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unsigned int ram_size = s->ram_size / MiB;
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while (socket < 6) {
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if (ram_size >= 64) {
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s->simm_size[socket] = 32;
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s->simm_size[socket + 1] = 32;
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ram_size -= 64;
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} else if (ram_size >= 16) {
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s->simm_size[socket] = 8;
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s->simm_size[socket + 1] = 8;
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ram_size -= 16;
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} else {
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/* Not enough memory */
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break;
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}
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socket += 2;
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}
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for (socket = 0; socket < 6; socket++) {
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if (s->simm_size[socket]) {
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char name[] = "simm.?";
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name[5] = socket + '0';
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memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
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name,
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s->simm_size[socket] * MiB);
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memory_region_add_subregion_overlap(get_system_memory(), 0,
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&s->simm[socket], socket);
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}
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}
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if (ram_size) {
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/* unable to push all requested RAM in SIMMs */
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error_setg(errp, "RAM size incompatible with this board. "
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"Try again with something else, like %" PRId64 " MB",
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s->ram_size / MiB - ram_size);
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return;
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}
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if (s->autoconfigure) {
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uint32_t start_address = 0;
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for (socket = 0; socket < 6; socket++) {
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if (s->simm_size[socket]) {
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memory_region_set_enabled(&s->simm[socket], true);
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memory_region_set_address(&s->simm[socket], start_address);
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start_address += memory_region_size(&s->simm[socket]);
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}
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}
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}
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isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
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rs6000mc_port_list, s, "rs6000mc");
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}
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static const VMStateDescription vmstate_rs6000mc = {
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.name = "rs6000-mc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(port0820_index, RS6000MCState),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property rs6000mc_properties[] = {
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DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
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DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
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DEFINE_PROP_END_OF_LIST()
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};
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static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rs6000mc_realize;
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dc->vmsd = &vmstate_rs6000mc;
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dc->props = rs6000mc_properties;
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}
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static const TypeInfo rs6000mc_info = {
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.name = TYPE_RS6000MC,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(RS6000MCState),
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.class_init = rs6000mc_class_initfn,
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};
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static void rs6000mc_types(void)
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{
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type_register_static(&rs6000mc_info);
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}
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type_init(rs6000mc_types)
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