mirror of https://gitee.com/openkylin/qemu.git
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SOC_H
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#define ASPEED_SOC_H
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#include "hw/arm/arm.h"
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#include "hw/intc/aspeed_vic.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/net/ftgmac100.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_WDTS_NUM 3
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typedef struct AspeedSoCState {
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/*< private >*/
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DeviceState parent;
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/*< public >*/
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ARMCPU cpu;
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MemoryRegion sram;
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AspeedVICState vic;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedSCUState scu;
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AspeedSMCState fmc;
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AspeedSMCState spi[ASPEED_SPIS_NUM];
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AspeedSDMCState sdmc;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100;
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} AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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typedef struct AspeedSoCInfo {
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const char *name;
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const char *cpu_type;
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uint32_t silicon_rev;
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hwaddr sdram_base;
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uint64_t sram_size;
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int spis_num;
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const hwaddr *spi_bases;
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const char *fmc_typename;
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const char **spi_typename;
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int wdts_num;
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} AspeedSoCInfo;
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typedef struct AspeedSoCClass {
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DeviceClass parent_class;
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AspeedSoCInfo *info;
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} AspeedSoCClass;
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#define ASPEED_SOC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
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#define ASPEED_SOC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
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#endif /* ASPEED_SOC_H */
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