Roman Kapl 93bf9a4273 tcg/i386: fix vector operations on 32-bit hosts ... The TCG backend uses LOWREGMASK to get the low 3 bits of register numbers. This was defined as no-op for 32-bit x86, with the assumption that we have eight registers anyway. This assumption is not true once we have xmm regs. Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes and have overflown into other opcode fields, wreaking havoc. To trigger these problems, you can try running the "movi d8, #0x0" AArch64 instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated, but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2". Fixes: 770c2fc7bb ("Add vector operations") Signed-off-by: Roman Kapl <rka@sysgo.com> Message-Id: <20180824131734.18557-1-rka@sysgo.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2018-09-26 09:02:51 -07:00
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tcg-target.h	tcg/i386: Add vector operations	2018-02-08 15:54:08 +00:00
tcg-target.inc.c	tcg/i386: fix vector operations on 32-bit hosts	2018-09-26 09:02:51 -07:00
tcg-target.opc.h	tcg/i386: Add vector operations	2018-02-08 15:54:08 +00:00