mirror of https://gitee.com/openkylin/qemu.git
f00f57f344
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
-----BEGIN PGP SIGNATURE-----
iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAl9aa4YACgkQIeENKd+X
cFTJjgf5ASfFIO5HqP1l80/UM5Pswyq0IROZDq0ItZa6U4EPzLXoE2N0POriIj4h
Ds2JbMg0ORDqY0VbSxHlgYHMgJ9S6cuVOMnATsPG0d2jaJ3gSxLBu5k/1ENqe+Vw
sSYXZv5uEAUfOFz99zbuhKHct5HzlmBFW9dVHdflUQS+cRgsSXq27mz1BvZ8xMWl
lMhwubqdoNx0rOD3vKnlwrxaf54DcJ2IQT3BtTCjEar3tukdNaLijAuwt2hrFyr+
IwpeFXA/NWar+mXP3M+BvcLaI33j73/ac2+S5SJuzHGp/ot5nT5gAuq3PDEjHMeS
t6z9Exp776VXxNE2iUA5NB65Yp3/6w==
=07oA
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging
This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
- Allows 16-bit writes to the SiFive test device. This fixes the
failure to reboot the RISC-V virt machine
- Support for the Microchip PolarFire SoC and Icicle Kit
- A reafactor of RISC-V code out of hw/riscv
# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
hw/riscv: Sort the Kconfig options in alphabetical order
hw/riscv: Drop CONFIG_SIFIVE
hw/riscv: Always build riscv_hart.c
hw/riscv: Move sifive_test model to hw/misc
hw/riscv: Move sifive_uart model to hw/char
hw/riscv: Move riscv_htif model to hw/char
hw/riscv: Move sifive_plic model to hw/intc
hw/riscv: Move sifive_clint model to hw/intc
hw/riscv: Move sifive_gpio model to hw/gpio
hw/riscv: Move sifive_u_otp model to hw/misc
hw/riscv: Move sifive_u_prci model to hw/misc
hw/riscv: Move sifive_e_prci model to hw/misc
hw/riscv: sifive_u: Connect a DMA controller
hw/riscv: clint: Avoid using hard-coded timebase frequency
hw/riscv: microchip_pfsoc: Hook GPIO controllers
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
hw/net: cadence_gem: Add a new 'phy-addr' property
hw/riscv: microchip_pfsoc: Connect a DMA controller
hw/dma: Add SiFive platform DMA controller emulation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/riscv/trace-events
|
||
|---|---|---|
| .. | ||
| Kconfig | ||
| allwinner-a10.c | ||
| allwinner-h3.c | ||
| armsse.c | ||
| armv7m.c | ||
| aspeed.c | ||
| aspeed_ast2600.c | ||
| aspeed_soc.c | ||
| bcm2835_peripherals.c | ||
| bcm2836.c | ||
| boot.c | ||
| collie.c | ||
| cubieboard.c | ||
| digic.c | ||
| digic_boards.c | ||
| exynos4_boards.c | ||
| exynos4210.c | ||
| fsl-imx6.c | ||
| fsl-imx6ul.c | ||
| fsl-imx7.c | ||
| fsl-imx25.c | ||
| fsl-imx31.c | ||
| gumstix.c | ||
| highbank.c | ||
| imx25_pdk.c | ||
| integratorcp.c | ||
| kzm.c | ||
| mainstone.c | ||
| mcimx6ul-evk.c | ||
| mcimx7d-sabre.c | ||
| meson.build | ||
| microbit.c | ||
| mps2-tz.c | ||
| mps2.c | ||
| msf2-soc.c | ||
| msf2-som.c | ||
| musca.c | ||
| musicpal.c | ||
| netduino2.c | ||
| netduinoplus2.c | ||
| nrf51_soc.c | ||
| nseries.c | ||
| omap1.c | ||
| omap2.c | ||
| omap_sx1.c | ||
| orangepi.c | ||
| palm.c | ||
| pxa2xx.c | ||
| pxa2xx_gpio.c | ||
| pxa2xx_pic.c | ||
| raspi.c | ||
| realview.c | ||
| sabrelite.c | ||
| sbsa-ref.c | ||
| smmu-common.c | ||
| smmu-internal.h | ||
| smmuv3-internal.h | ||
| smmuv3.c | ||
| spitz.c | ||
| stellaris.c | ||
| stm32f205_soc.c | ||
| stm32f405_soc.c | ||
| strongarm.c | ||
| strongarm.h | ||
| sysbus-fdt.c | ||
| tosa.c | ||
| trace-events | ||
| trace.h | ||
| versatilepb.c | ||
| vexpress.c | ||
| virt-acpi-build.c | ||
| virt.c | ||
| xilinx_zynq.c | ||
| xlnx-versal-virt.c | ||
| xlnx-versal.c | ||
| xlnx-zcu102.c | ||
| xlnx-zynqmp.c | ||
| z2.c | ||