!27 修复v11龙芯QProcess接口异常问题
Merge pull request !27 from renjianquan/openkylin/nile
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2c5576500e
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@ -1,3 +1,11 @@
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qtbase-opensource-src (5.15.10+dfsg-3ok2.10) nile; urgency=medium
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* BUG号:无
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* 需求号:无
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* 其他更改:修复v11龙芯QProcess接口异常问题——Add macro definition loongarch64
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-- renjianquan <renjianquan@kylinos.cn> Tue, 08 Oct 2024 11:39:39 +0800
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qtbase-opensource-src (5.15.10+dfsg-3ok2.9) nile; urgency=medium
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qtbase-opensource-src (5.15.10+dfsg-3ok2.9) nile; urgency=medium
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* BUG号:无
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* BUG号:无
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@ -82,7 +82,8 @@ static int sys_clone(unsigned long cloneflags, int *ptid)
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return syscall(__NR_clone, cloneflags, child_stack, stack_size, ptid, newtls, ctid);
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return syscall(__NR_clone, cloneflags, child_stack, stack_size, ptid, newtls, ctid);
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#elif defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__mips__) || \
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#elif defined(__arc__) || defined(__arm__) || defined(__aarch64__) || defined(__mips__) || \
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defined(__nds32__) || defined(__hppa__) || defined(__powerpc__) || defined(__i386__) || \
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defined(__nds32__) || defined(__hppa__) || defined(__powerpc__) || defined(__i386__) || \
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defined(__x86_64__) || defined(__xtensa__) || defined(__alpha__) || defined(__riscv)
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defined(__x86_64__) || defined(__xtensa__) || defined(__alpha__) || defined(__riscv) || \
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defined(loongarch64)
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/* ctid and newtls are inverted on CONFIG_CLONE_BACKWARDS architectures,
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/* ctid and newtls are inverted on CONFIG_CLONE_BACKWARDS architectures,
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* but since both values are 0, there's no harm. */
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* but since both values are 0, there's no harm. */
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return syscall(__NR_clone, cloneflags, child_stack, ptid, ctid, newtls);
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return syscall(__NR_clone, cloneflags, child_stack, ptid, ctid, newtls);
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