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qtwebengine-opensource-src
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try to build riscv64

This commit is contained in:
韩品龙 2023-10-08 15:45:28 +08:00
parent 8c6699b198
commit dc6fabe510
74 changed files with 2449 additions and 98 deletions
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1
configure.pri
View File

@ -148,6 +148,7 @@ defineTest(qtConfTest_detectArch) {
contains(QT_ARCH, "arm")|contains(QT_ARCH, "arm64"): return(true)
contains(QT_ARCH, "mips"): return(true)
contains(QT_ARCH, "mips64"): return(true)
contains(QT_ARCH, "riscv64"): return(true)
qtLog("Architecture not supported.")
return(false)
}

28
debian/control vendored
View File

@ -98,7 +98,7 @@ Vcs-Git: https://salsa.debian.org/qt-kde-team/qt/qtwebengine.git
Homepage: https://doc.qt.io/qt-5/qtwebengine-index.html
Package: qtwebengine5-dev
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Section: libdevel
Depends: libqt5webchannel5-dev,
@ -119,7 +119,7 @@ Description: Web content engine library for Qt - development files
using QtWebEngine library.
Package: qtwebengine5-private-dev
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Section: libdevel
Depends: qtwebengine5-dev (= ${binary:Version}), ${misc:Depends}
@ -131,7 +131,7 @@ Description: Web content engine library for Qt - private development files
Qt 5 applications using QtWebEngine library.
Package: qtpdf5-dev
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Section: libdevel
Depends: libqt5pdf5 (= ${binary:Version}),
@ -146,7 +146,7 @@ Description: Qt 5 PDF library - development files
using Qt PDF library.
Package: libqt5webengine5
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: libqt5webengine-data (= ${source:Version}),
${misc:Depends},
@ -159,7 +159,7 @@ Description: Web content engine library for Qt
This package contains the QtWebEngine library.
Package: libqt5webenginecore5
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Provides: qtwebengine-abi-5-15-9
Depends: libqt5webengine-data (= ${source:Version}),
@ -176,7 +176,7 @@ Description: Web content engine library for Qt - Core
This package contains the core QtWebEngine library.
Package: libqt5webenginewidgets5
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: libqt5webengine-data (= ${source:Version}),
${misc:Depends},
@ -189,7 +189,7 @@ Description: Web content engine library for Qt - Widget
This package contains the widget QtWebEngine library.
Package: libqt5pdf5
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: ${misc:Depends}, ${shlibs:Depends}
Description: Qt 5 PDF library
@ -198,7 +198,7 @@ Description: Qt 5 PDF library
This package contains the Qt PDF library.
Package: libqt5pdfwidgets5
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: ${misc:Depends}, ${shlibs:Depends}
Description: Qt 5 PDF Widgets library
@ -218,7 +218,7 @@ Description: Web content engine library for Qt - Data
This package contains the arch independent parts of QtWebEngine libraries.
Package: qt5-image-formats-plugin-pdf
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: ${misc:Depends}, ${shlibs:Depends}
Description: Qt 5 PDF image format plugin
@ -228,7 +228,7 @@ Description: Qt 5 PDF image format plugin
to view PDF files (the first page of PDF will be shown).
Package: qml-module-qtwebengine
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: qml-module-qtquick2, ${misc:Depends}, ${shlibs:Depends}
Pre-Depends: ${misc:Pre-Depends}
@ -239,7 +239,7 @@ Description: Qt WebEngine QML module
This package contains the WebEngine QML module for QtDeclarative.
Package: qml-module-qtquick-pdf
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: qml-module-qtgraphicaleffects (>= 5.12),
qml-module-qtquick-controls2 (>= 5.14),
@ -256,7 +256,7 @@ Description: Qt Quick PDF QML module
This package contains the Qt Quick PDF QML module.
Package: qtwebengine5-dev-tools
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: foreign
Section: devel
Depends: qtchooser, ${misc:Depends}, ${shlibs:Depends}
@ -269,7 +269,7 @@ Description: Qt WebEngine tools
in Qt WebEngine.
Package: qtwebengine5-examples
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: libjs-jquery,
libjs-marked,
@ -289,7 +289,7 @@ Description: Qt WebEngine - Examples
This package contains the WebEngine examples.
Package: qtpdf5-examples
Architecture: amd64 arm64 armhf i386 mips64el mipsel
Architecture: amd64 arm64 armhf i386 mips64el mipsel riscv64
Multi-Arch: same
Depends: qml-module-qtquick-pdf (= ${binary:Version}),
${misc:Depends},

6
debian/rules vendored
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@ -35,7 +35,7 @@ gstab_architectures :=
fulldebug_architectures :=
small_architectures := armhf mipsel
no_gold_architectures := arm64 armhf mipsel
no_gold_architectures := arm64 armhf mipsel riscv64
config_args = -proprietary-codecs \
-feature-webengine-system-libvpx \
@ -75,6 +75,10 @@ override_dh_auto_configure:
qmake QT_BUILD_PARTS+=tests QMAKE_EXTRA_ARGS+="$(config_args)" QMAKE_PYTHON2=python2
# Enable gstabs debugging symbols only on gstab_architectures.
ifeq ($(DEB_HOST_ARCH),riscv64)
echo "QT_ARCH = riscv64" >> .qmake.conf
endif
ifeq ($(DEB_HOST_ARCH),$(findstring $(DEB_HOST_ARCH), $(gstab_architectures)))
echo "QMAKE_CXXFLAGS -= -g" >> .qmake.conf
echo "QMAKE_CXXFLAGS += -gstabs" >> .qmake.conf

1
mkspecs/features/functions.prf
View File

@ -107,6 +107,7 @@ defineReplace(gnArch) {
contains(qtArch, "mips"): return(mipsel)
contains(qtArch, "mips64"): return(mips64el)
contains(qtArch, "mips64el"): return(mips64el)
contains(qtArch, "riscv64"): return(riscv64)
return(unknown)
}

2
src/3rdparty/chromium/base/process/launch_posix.cc vendored
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@ -704,7 +704,7 @@ NOINLINE pid_t CloneAndLongjmpInChild(unsigned long flags,
alignas(16) char stack_buf[PTHREAD_STACK_MIN];
#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \
defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_S390_FAMILY) || \
defined(ARCH_CPU_PPC64_FAMILY)
defined(ARCH_CPU_PPC64_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
// The stack grows downward.
void* stack = stack_buf + sizeof(stack_buf);
#else

5
src/3rdparty/chromium/build/build_config.h vendored
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@ -193,6 +193,11 @@
#define ARCH_CPU_32_BITS 1
#define ARCH_CPU_BIG_ENDIAN 1
#endif
#elif defined(__riscv) && __riscv_xlen == 64
#define ARCH_CPU_RISCV_FAMILY 1
#define ARCH_CPU_RISCV64 1
#define ARCH_CPU_64_BITS 1
#define ARCH_CPU_LITTLE_ENDIAN 1
#else
#error Please add support for your architecture in build/build_config.h
#endif

17
src/3rdparty/chromium/build/toolchain/linux/BUILD.gn vendored
View File

@ -298,3 +298,20 @@ gcc_toolchain("mips64") {
is_clang = false
}
}
gcc_toolchain("riscv64") {
cc = "gcc"
cxx = "g++"
readelf = "readelf"
nm = "nm"
ar = "ar"
ld = cxx
toolchain_args = {
current_cpu = "riscv64"
current_os = "linux"
is_clang = false
}
}

3
src/3rdparty/chromium/sandbox/features.gni vendored
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@ -11,7 +11,8 @@ import("//build/config/nacl/config.gni")
use_seccomp_bpf = (is_linux || is_chromeos || is_android) &&
(current_cpu == "x86" || current_cpu == "x64" ||
current_cpu == "arm" || current_cpu == "arm64" ||
current_cpu == "mipsel" || current_cpu == "mips64el")
current_cpu == "mipsel" || current_cpu == "mips64el" ||
current_cpu == "riscv64")
use_seccomp_bpf = use_seccomp_bpf || is_nacl_nonsfi

6
src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h vendored
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@ -49,6 +49,12 @@
#define MAX_PUBLIC_SYSCALL __NR_syscalls
#define MAX_SYSCALL MAX_PUBLIC_SYSCALL
#elif defined(__riscv)
#define MIN_SYSCALL 0u
#define MAX_PUBLIC_SYSCALL 1024u
#define MAX_SYSCALL MAX_PUBLIC_SYSCALL
#else
#error "Unsupported architecture"
#endif

40
src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h vendored
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@ -346,6 +346,46 @@ struct regs_struct {
#define SECCOMP_PT_PARM4(_regs) (_regs).regs[3]
#define SECCOMP_PT_PARM5(_regs) (_regs).regs[4]
#define SECCOMP_PT_PARM6(_regs) (_regs).regs[5]
#elif defined(__riscv)
struct regs_struct {
unsigned long regs[32];
};
#define SECCOMP_ARCH AUDIT_ARCH_RISCV64
#define SECCOMP_REG(_ctx, _reg) ((_ctx)->uc_mcontext.__gregs[_reg])
#define SECCOMP_RESULT(_ctx) SECCOMP_REG(_ctx, REG_A0)
#define SECCOMP_SYSCALL(_ctx) SECCOMP_REG(_ctx, REG_A0+7)
#define SECCOMP_IP(_ctx) (_ctx)->uc_mcontext.__gregs[REG_PC]
#define SECCOMP_PARM1(_ctx) SECCOMP_REG(_ctx, REG_A0)
#define SECCOMP_PARM2(_ctx) SECCOMP_REG(_ctx, REG_A0+1)
#define SECCOMP_PARM3(_ctx) SECCOMP_REG(_ctx, REG_A0+2)
#define SECCOMP_PARM4(_ctx) SECCOMP_REG(_ctx, REG_A0+3)
#define SECCOMP_PARM5(_ctx) SECCOMP_REG(_ctx, REG_A0+4)
#define SECCOMP_PARM6(_ctx) SECCOMP_REG(_ctx, REG_A0+5)
#define SECCOMP_NR_IDX (offsetof(struct arch_seccomp_data, nr))
#define SECCOMP_ARCH_IDX (offsetof(struct arch_seccomp_data, arch))
#define SECCOMP_IP_MSB_IDX \
(offsetof(struct arch_seccomp_data, instruction_pointer) + 4)
#define SECCOMP_IP_LSB_IDX \
(offsetof(struct arch_seccomp_data, instruction_pointer) + 0)
#define SECCOMP_ARG_MSB_IDX(nr) \
(offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 4)
#define SECCOMP_ARG_LSB_IDX(nr) \
(offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 0)
#define SECCOMP_PT_RESULT(_regs) (_regs).regs[REG_A0]
#define SECCOMP_PT_SYSCALL(_regs) (_regs).regs[REG_A0+7]
#define SECCOMP_PT_IP(_regs) (_regs).regs[REG_PC]
#define SECCOMP_PT_PARM1(_regs) (_regs).regs[REG_A0]
#define SECCOMP_PT_PARM2(_regs) (_regs).regs[REG_A0+1]
#define SECCOMP_PT_PARM3(_regs) (_regs).regs[REG_A0+2]
#define SECCOMP_PT_PARM4(_regs) (_regs).regs[REG_A0+3]
#define SECCOMP_PT_PARM5(_regs) (_regs).regs[REG_A0+4]
#define SECCOMP_PT_PARM6(_regs) (_regs).regs[REG_A0+5]
#else
#error Unsupported target platform

9
src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc vendored
View File

@ -58,6 +58,9 @@ bool IsBaselinePolicyAllowed(int sysno) {
#endif
#if defined(__mips__)
SyscallSets::IsMipsPrivate(sysno) ||
#endif
#if defined(__riscv)
SyscallSets::IsRiscvPrivate(sysno) ||
#endif
SyscallSets::IsAllowedOperationOnFd(sysno);
}
@ -181,7 +184,7 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno,
return RestrictFcntlCommands();
#endif
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
// fork() is never used as a system call (clone() is used instead), but we
// have seen it in fallback code on Android.
if (sysno == __NR_fork) {
@ -231,7 +234,7 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno,
}
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
if (sysno == __NR_mmap)
return RestrictMmapFlags();
#endif
@ -249,7 +252,7 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno,
return RestrictPrctl();
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
if (sysno == __NR_socketpair) {
// Only allow AF_UNIX, PF_UNIX. Crash if anything else is seen.
static_assert(AF_UNIX == PF_UNIX,

4
src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc vendored
View File

@ -37,7 +37,7 @@
#include <sys/ioctl.h>
#include <sys/ptrace.h>
#if defined(OS_LINUX) && !defined(OS_CHROMEOS) && !defined(__arm__) && \
!defined(__aarch64__) && !defined(PTRACE_GET_THREAD_AREA)
!defined(__aarch64__) && !defined(__riscv) && !defined(PTRACE_GET_THREAD_AREA)
// Also include asm/ptrace-abi.h since ptrace.h in older libc (for instance
// the one in Ubuntu 16.04 LTS) is missing PTRACE_GET_THREAD_AREA.
// asm/ptrace-abi.h doesn't exist on arm32 and PTRACE_GET_THREAD_AREA isn't
@ -410,7 +410,7 @@ ResultExpr RestrictPrlimitToGetrlimit(pid_t target_pid) {
ResultExpr RestrictPtrace() {
const Arg<int> request(0);
return Switch(request).CASES((
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
PTRACE_GETREGS,
PTRACE_GETFPREGS,
#if defined(TRACE_GET_THREAD_AREA)

73
src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc vendored
View File

@ -86,7 +86,7 @@ bool SyscallSets::IsUmask(int sysno) {
// Both EPERM and ENOENT are valid errno unless otherwise noted in comment.
bool SyscallSets::IsFileSystem(int sysno) {
switch (sysno) {
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_access: // EPERM not a valid errno.
case __NR_chmod:
case __NR_chown:
@ -118,7 +118,7 @@ bool SyscallSets::IsFileSystem(int sysno) {
case __NR_faccessat: // EPERM not a valid errno.
case __NR_fchmodat:
case __NR_fchownat: // Should be called chownat ?
#if defined(__x86_64__) || defined(__aarch64__)
#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv)
case __NR_newfstatat: // fstatat(). EPERM not a valid errno.
#elif defined(__i386__) || defined(__arm__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS))
@ -201,7 +201,7 @@ bool SyscallSets::IsAllowedFileSystemAccessViaFd(int sysno) {
case __NR_oldfstat:
#endif
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_sync_file_range: // EPERM not a valid errno.
#elif defined(__arm__)
case __NR_arm_sync_file_range: // EPERM not a valid errno.
@ -225,7 +225,7 @@ bool SyscallSets::IsDeniedFileSystemAccessViaFd(int sysno) {
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS))
case __NR_ftruncate64:
#endif
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_getdents: // EPERM not a valid errno.
#endif
case __NR_getdents64: // EPERM not a valid errno.
@ -304,7 +304,7 @@ bool SyscallSets::IsProcessPrivilegeChange(int sysno) {
bool SyscallSets::IsProcessGroupOrSession(int sysno) {
switch (sysno) {
case __NR_setpgid:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_getpgrp:
#endif
case __NR_setsid:
@ -333,7 +333,7 @@ bool SyscallSets::IsAllowedSignalHandling(int sysno) {
case __NR_rt_sigsuspend:
case __NR_rt_tgsigqueueinfo:
case __NR_sigaltstack:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_signalfd:
#endif
case __NR_signalfd4:
@ -357,12 +357,12 @@ bool SyscallSets::IsAllowedOperationOnFd(int sysno) {
switch (sysno) {
case __NR_close:
case __NR_dup:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_dup2:
#endif
case __NR_dup3:
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_shutdown:
#endif
return true;
@ -401,7 +401,7 @@ bool SyscallSets::IsAllowedProcessStartOrDeath(int sysno) {
return true;
case __NR_clone: // Should be parameter-restricted.
case __NR_setns: // Privileged.
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_fork:
#endif
#if defined(__i386__) || defined(__x86_64__)
@ -412,7 +412,7 @@ bool SyscallSets::IsAllowedProcessStartOrDeath(int sysno) {
#endif
case __NR_set_tid_address:
case __NR_unshare:
#if !defined(__mips__) && !defined(__aarch64__)
#if !defined(__mips__) && !defined(__aarch64__) && !defined(__riscv)
case __NR_vfork:
#endif
default:
@ -433,7 +433,7 @@ bool SyscallSets::IsAllowedFutex(int sysno) {
bool SyscallSets::IsAllowedEpoll(int sysno) {
switch (sysno) {
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_epoll_create:
case __NR_epoll_wait:
#endif
@ -454,14 +454,14 @@ bool SyscallSets::IsAllowedEpoll(int sysno) {
bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) {
switch (sysno) {
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_pipe:
#endif
case __NR_pipe2:
return true;
default:
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_socketpair: // We will want to inspect its argument.
#endif
return false;
@ -471,7 +471,7 @@ bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) {
bool SyscallSets::IsDeniedGetOrModifySocket(int sysno) {
switch (sysno) {
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_accept:
case __NR_accept4:
case __NR_bind:
@ -525,7 +525,7 @@ bool SyscallSets::IsAllowedAddressSpaceAccess(int sysno) {
case __NR_mincore:
case __NR_mlockall:
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_mmap:
#endif
#if defined(__i386__) || defined(__arm__) || \
@ -558,7 +558,7 @@ bool SyscallSets::IsAllowedGeneralIo(int sysno) {
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS))
case __NR__llseek:
#endif
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_poll:
#endif
case __NR_ppoll:
@ -571,7 +571,7 @@ bool SyscallSets::IsAllowedGeneralIo(int sysno) {
case __NR_recv:
#endif
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_recvfrom: // Could specify source.
case __NR_recvmsg: // Could specify source.
#endif
@ -586,7 +586,7 @@ bool SyscallSets::IsAllowedGeneralIo(int sysno) {
case __NR_send:
#endif
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_sendmsg: // Could specify destination.
case __NR_sendto: // Could specify destination.
#endif
@ -636,7 +636,7 @@ bool SyscallSets::IsSeccomp(int sysno) {
bool SyscallSets::IsAllowedBasicScheduler(int sysno) {
switch (sysno) {
case __NR_sched_yield:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_pause:
#endif
case __NR_nanosleep:
@ -720,7 +720,7 @@ bool SyscallSets::IsNuma(int sysno) {
case __NR_getcpu:
case __NR_mbind:
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_migrate_pages:
#endif
case __NR_move_pages:
@ -749,7 +749,7 @@ bool SyscallSets::IsGlobalProcessEnvironment(int sysno) {
switch (sysno) {
case __NR_acct: // Privileged.
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
case __NR_getrlimit:
#endif
#if defined(__i386__) || defined(__arm__)
@ -784,7 +784,7 @@ bool SyscallSets::IsDebug(int sysno) {
bool SyscallSets::IsGlobalSystemStatus(int sysno) {
switch (sysno) {
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR__sysctl:
case __NR_sysfs:
#endif
@ -802,7 +802,7 @@ bool SyscallSets::IsGlobalSystemStatus(int sysno) {
bool SyscallSets::IsEventFd(int sysno) {
switch (sysno) {
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_eventfd:
#endif
case __NR_eventfd2:
@ -838,7 +838,8 @@ bool SyscallSets::IsKeyManagement(int sysno) {
}
#if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
bool SyscallSets::IsSystemVSemaphores(int sysno) {
switch (sysno) {
case __NR_semctl:
@ -854,7 +855,8 @@ bool SyscallSets::IsSystemVSemaphores(int sysno) {
#if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \
defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
// These give a lot of ambient authority and bypass the setuid sandbox.
bool SyscallSets::IsSystemVSharedMemory(int sysno) {
switch (sysno) {
@ -870,7 +872,8 @@ bool SyscallSets::IsSystemVSharedMemory(int sysno) {
#endif
#if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
bool SyscallSets::IsSystemVMessageQueue(int sysno) {
switch (sysno) {
case __NR_msgctl:
@ -901,7 +904,8 @@ bool SyscallSets::IsSystemVIpc(int sysno) {
bool SyscallSets::IsAnySystemV(int sysno) {
#if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
return IsSystemVMessageQueue(sysno) || IsSystemVSemaphores(sysno) ||
IsSystemVSharedMemory(sysno);
#elif defined(__i386__) || \
@ -934,7 +938,7 @@ bool SyscallSets::IsAdvancedScheduler(int sysno) {
bool SyscallSets::IsInotify(int sysno) {
switch (sysno) {
case __NR_inotify_add_watch:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_inotify_init:
#endif
case __NR_inotify_init1:
@ -1065,7 +1069,7 @@ bool SyscallSets::IsMisc(int sysno) {
#if defined(__x86_64__)
case __NR_tuxcall:
#endif
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_vserver:
#endif
return true;
@ -1100,6 +1104,17 @@ bool SyscallSets::IsArmPrivate(int sysno) {
}
#endif // defined(__arm__)
#if defined(__riscv)
bool SyscallSets::IsRiscvPrivate(int sysno) {
switch (sysno) {
case __NR_riscv_flush_icache:
return true;
default:
return false;
}
}
#endif // defined(__riscv)
#if defined(__mips__)
bool SyscallSets::IsMipsPrivate(int sysno) {
switch (sysno) {

14
src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h vendored
View File

@ -49,7 +49,7 @@ class SANDBOX_EXPORT SyscallSets {
#endif
#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
static bool IsNetworkSocketInformation(int sysno);
#endif
@ -72,18 +72,21 @@ class SANDBOX_EXPORT SyscallSets {
static bool IsAsyncIo(int sysno);
static bool IsKeyManagement(int sysno);
#if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
static bool IsSystemVSemaphores(int sysno);
#endif
#if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \
defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
// These give a lot of ambient authority and bypass the setuid sandbox.
static bool IsSystemVSharedMemory(int sysno);
#endif
#if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS))
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \
defined(__riscv)
static bool IsSystemVMessageQueue(int sysno);
#endif
@ -110,6 +113,9 @@ class SANDBOX_EXPORT SyscallSets {
static bool IsMipsPrivate(int sysno);
static bool IsMipsMisc(int sysno);
#endif // defined(__mips__)
#if defined(__riscv)
static bool IsRiscvPrivate(int sysno);
#endif
private:
DISALLOW_IMPLICIT_CONSTRUCTORS(SyscallSets);
};

34
src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc vendored
View File

@ -18,7 +18,7 @@ namespace sandbox {
namespace {
#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \
defined(ARCH_CPU_MIPS_FAMILY)
defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
// Number that's not currently used by any Linux kernel ABIs.
const int kInvalidSyscallNumber = 0x351d3;
#else
@ -312,6 +312,28 @@ asm(// We need to be able to tell the kernel exactly where we made a
"2:ret\n"
".cfi_endproc\n"
".size SyscallAsm, .-SyscallAsm\n"
#elif defined(__riscv)
".text\n"
".align 2\n"
".type SyscallAsm, %function\n"
"SyscallAsm:\n"
".cfi_startproc\n"
"bgez a0,1f\n"
"lla a0,2f\n"
"j 2f\n"
"1:mv a7, a0\n"
"ld a0, (a1)\n"
"ld a2, 16(a1)\n"
"ld a3, 24(a1)\n"
"ld a4, 32(a1)\n"
"ld a5, 40(a1)\n"
"ld a6, 48(a1)\n"
"ld a1, 8(a1)\n"
// Enter the kernel
"scall\n"
"2:ret\n"
".cfi_endproc\n"
".size SyscallAsm, .-SyscallAsm\n"
#endif
); // asm
@ -323,6 +345,10 @@ intptr_t SyscallAsm(intptr_t nr, const intptr_t args[6]);
extern "C" {
intptr_t SyscallAsm(intptr_t nr, const intptr_t args[8]);
}
#elif defined(__riscv)
extern "C" {
intptr_t SyscallAsm(intptr_t nr, const intptr_t args[7]);
}
#endif
} // namespace
@ -355,6 +381,10 @@ intptr_t Syscall::Call(int nr,
// where that makes sense.
#if defined(__mips__)
const intptr_t args[8] = {p0, p1, p2, p3, p4, p5, p6, p7};
#elif defined(__riscv)
DCHECK_EQ(p7, 0) << " Support for syscalls with more than seven arguments "
"not added for this architecture";
const intptr_t args[7] = {p0, p1, p2, p3, p4, p5, p6};
#else
DCHECK_EQ(p6, 0) << " Support for syscalls with more than six arguments not "
"added for this architecture";
@ -429,6 +459,8 @@ intptr_t Syscall::Call(int nr,
ret = inout;
}
#elif defined(__riscv)
intptr_t ret = SyscallAsm(nr, args);
#else
#error "Unimplemented architecture"
#endif

2
src/3rdparty/chromium/sandbox/linux/services/credentials.cc vendored
View File

@ -81,7 +81,7 @@ bool ChrootToSafeEmptyDir() {
pid_t pid = -1;
alignas(16) char stack_buf[PTHREAD_STACK_MIN];
#if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \
defined(ARCH_CPU_MIPS_FAMILY)
defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
// The stack grows downward.
void* stack = stack_buf + sizeof(stack_buf);
#else

2
src/3rdparty/chromium/sandbox/linux/services/syscall_wrappers.cc vendored
View File

@ -61,7 +61,7 @@ long sys_clone(unsigned long flags,
#if defined(ARCH_CPU_X86_64)
return syscall(__NR_clone, flags, child_stack, ptid, ctid, tls);
#elif defined(ARCH_CPU_X86) || defined(ARCH_CPU_ARM_FAMILY) || \
defined(ARCH_CPU_MIPS_FAMILY)
defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY)
// CONFIG_CLONE_BACKWARDS defined.
return syscall(__NR_clone, flags, child_stack, ptid, tls, ctid);
#endif

18
src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc vendored
View File

@ -128,43 +128,43 @@ bool BrokerProcess::IsSyscallBrokerable(int sysno, bool fast_check) const {
// and are default disabled in Android. So, we should refuse to broker them
// to be consistent with the platform's restrictions.
switch (sysno) {
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_access:
#endif
case __NR_faccessat:
return !fast_check || allowed_command_set_.test(COMMAND_ACCESS);
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_mkdir:
#endif
case __NR_mkdirat:
return !fast_check || allowed_command_set_.test(COMMAND_MKDIR);
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_open:
#endif
case __NR_openat:
return !fast_check || allowed_command_set_.test(COMMAND_OPEN);
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_readlink:
#endif
case __NR_readlinkat:
return !fast_check || allowed_command_set_.test(COMMAND_READLINK);
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_rename:
#endif
case __NR_renameat:
case __NR_renameat2:
return !fast_check || allowed_command_set_.test(COMMAND_RENAME);
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_rmdir:
return !fast_check || allowed_command_set_.test(COMMAND_RMDIR);
#endif
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_stat:
case __NR_lstat:
#endif
@ -174,7 +174,7 @@ bool BrokerProcess::IsSyscallBrokerable(int sysno, bool fast_check) const {
#if defined(__NR_fstatat64)
case __NR_fstatat64:
#endif
#if defined(__x86_64__) || defined(__aarch64__)
#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv)
case __NR_newfstatat:
#endif
return !fast_check || allowed_command_set_.test(COMMAND_STAT);
@ -189,7 +189,7 @@ bool BrokerProcess::IsSyscallBrokerable(int sysno, bool fast_check) const {
return !fast_check || allowed_command_set_.test(COMMAND_STAT);
#endif
#if !defined(__aarch64__) && !defined(OS_ANDROID)
#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv)
case __NR_unlink:
return !fast_check || allowed_command_set_.test(COMMAND_UNLINK);
#endif

6
src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h vendored
View File

@ -41,6 +41,9 @@
#ifndef EM_AARCH64
#define EM_AARCH64 183
#endif
#ifndef EM_RISCV
#define EM_RISCV 243
#endif
#ifndef __AUDIT_ARCH_64BIT
#define __AUDIT_ARCH_64BIT 0x80000000
@ -73,6 +76,9 @@
#ifndef AUDIT_ARCH_AARCH64
#define AUDIT_ARCH_AARCH64 (EM_AARCH64 | __AUDIT_ARCH_64BIT | __AUDIT_ARCH_LE)
#endif
#ifndef AUDIT_ARCH_RISCV64
#define AUDIT_ARCH_RISCV64 (EM_RISCV|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#endif
// For prctl.h
#ifndef PR_SET_SECCOMP

2
src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h vendored
View File

@ -13,7 +13,7 @@
// (not undefined, but defined different values and in different memory
// layouts). So, fill the gap here.
#if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \
defined(__aarch64__)
defined(__aarch64__) || defined(__riscv)
#define LINUX_SIGHUP 1
#define LINUX_SIGINT 2

2
src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h vendored
View File

@ -150,7 +150,7 @@ struct kernel_stat {
int st_blocks;
int st_pad4[14];
};
#elif defined(__aarch64__)
#elif defined(__aarch64__) || defined(__riscv)
struct kernel_stat {
unsigned long st_dev;
unsigned long st_ino;

4
src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h vendored
View File

@ -35,5 +35,9 @@
#include "sandbox/linux/system_headers/arm64_linux_syscalls.h"
#endif
#if defined(__riscv) && __riscv_xlen == 64
#include "sandbox/linux/system_headers/riscv64_linux_syscalls.h"
#endif
#endif // SANDBOX_LINUX_SYSTEM_HEADERS_LINUX_SYSCALLS_H_

1222
src/3rdparty/chromium/sandbox/linux/system_headers/riscv64_linux_syscalls.h vendored Normal file
View File

File diff suppressed because it is too large Load Diff

2
src/3rdparty/chromium/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc vendored
View File

@ -38,7 +38,7 @@ ResultExpr CrosAmdGpuProcessPolicy::EvaluateSyscall(int sysno) const {
case __NR_sched_setscheduler:
case __NR_sysinfo:
case __NR_uname:
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_readlink:
case __NR_stat:
#endif

2
src/3rdparty/chromium/sandbox/policy/linux/bpf_gpu_policy_linux.cc vendored
View File

@ -70,7 +70,7 @@ ResultExpr GpuProcessPolicy::EvaluateSyscall(int sysno) const {
(defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS))
case __NR_ftruncate64:
#endif
#if !defined(__aarch64__)
#if !defined(__aarch64__) && !defined(__riscv)
case __NR_getdents:
#endif
case __NR_getdents64:

2
src/3rdparty/chromium/sandbox/policy/linux/sandbox_seccomp_bpf_linux.cc vendored
View File

@ -64,7 +64,7 @@ using sandbox::bpf_dsl::ResultExpr;
// Make sure that seccomp-bpf does not get disabled by mistake. Also make sure
// that we think twice about this when adding a new architecture.
#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL)
#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL) && !defined(ARCH_CPU_RISCV64)
#error "Seccomp-bpf disabled on supported architecture!"
#endif // !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL)

2
src/3rdparty/chromium/skia/BUILD.gn vendored
View File

@ -821,6 +821,8 @@ skia_source_set("skia_opts") {
sources = skia_opts.none_sources
} else if (current_cpu == "s390x") {
sources = skia_opts.none_sources
} else if (current_cpu == "riscv64") {
sources = skia_opts.none_sources
} else {
assert(false, "Need to port cpu specific stuff from skia_library_opts.gyp")
}

2
src/3rdparty/chromium/third_party/angle/gni/angle.gni vendored
View File

@ -54,7 +54,7 @@ angle_data_dir = "angledata"
declare_args() {
if (current_cpu == "arm64" || current_cpu == "x64" ||
current_cpu == "mips64el" || current_cpu == "s390x" ||
current_cpu == "ppc64") {
current_cpu == "ppc64" || current_cpu == "riscv64") {
angle_64bit_current_cpu = true
} else if (current_cpu == "arm" || current_cpu == "x86" ||
current_cpu == "mipsel" || current_cpu == "s390" ||

1
src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h vendored
View File

@ -9,6 +9,7 @@
#ifndef ANGLE_PLATFORMMETHODS_H
#define ANGLE_PLATFORMMETHODS_H
#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <array>

2
src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn vendored
View File

@ -38,6 +38,8 @@ if (current_cpu == "x86" || current_cpu == "x64") {
sources = [ "SaveRegisters_mips64.S" ]
} else if (current_cpu == "ppc64") {
sources = [ "SaveRegisters_ppc64.S" ]
} else if (current_cpu == "riscv64") {
sources = [ "SaveRegisters_riscv64.S" ]
}
if (current_cpu == "arm") {

45
src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S vendored Normal file
View File

@ -0,0 +1,45 @@
/*
* typedef void (*PushAllRegistersCallback)(ThreadState*, intptr_t*);
* extern "C" void PushAllRegisters(ThreadState*, PushAllRegistersCallback)
*/
.type PushAllRegisters, %function
.global PushAllRegisters
.hidden PushAllRegisters
PushAllRegisters:
/* Push all callee-saves registers to get them
* on the stack for conservative stack scanning.
* Reserve space for callee-saved registers and return address.
*/
addi sp,sp,-112
/* Save the callee-saved registers and the return address. */
sd ra,0(sp)
sd s0,8(sp)
sd s1,16(sp)
sd s2,24(sp)
sd s3,32(sp)
sd s4,40(sp)
sd s5,48(sp)
sd s6,56(sp)
sd s7,64(sp)
sd s8,72(sp)
sd s9,80(sp)
sd s10,88(sp)
sd s11,96(sp)
/* Note: the callee-saved floating point registers do not need to be
* copied to the stack, because fp registers never hold heap pointers
* and so do not need to be kept visible to the garbage collector.
* Pass the first argument untouched in a0 and the
* stack pointer to the callback.
*/
mv ra,a1
mv a1,sp
jalr ra
/* Restore return address, adjust stack and return.
* Note: the copied registers do not need to be reloaded here,
* because they were preserved by the called routine.
*/
ld ra,0(sp)
addi sp,sp,112
ret
.size PushAllRegisters, . - PushAllRegisters

2
src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h vendored
View File

@ -105,6 +105,8 @@ extern "C" {
#elif defined(__mips__) && defined(__LP64__)
#define OPENSSL_64_BIT
#define OPENSSL_MIPS64
#elif defined(__riscv) && __SIZEOF_POINTER__ == 8
#define OPENSSL_64_BIT
#elif defined(__pnacl__)
#define OPENSSL_32_BIT
#define OPENSSL_PNACL

2
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h vendored
View File

@ -44,6 +44,8 @@ typedef MDRawContextARM RawContextCPU;
typedef MDRawContextARM64_Old RawContextCPU;
#elif defined(__mips__)
typedef MDRawContextMIPS RawContextCPU;
#elif defined(__riscv)
typedef MDRawContextRISCV64 RawContextCPU;
#else
#error "This code has not been ported to your platform yet."
#endif

28
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc vendored
View File

@ -270,7 +270,23 @@ void ThreadInfo::FillCPUContext(RawContextCPU* out) const {
out->float_save.fir = mcontext.fpc_eir;
#endif
}
#endif // __mips__
#elif defined(__riscv)
uintptr_t ThreadInfo::GetInstructionPointer() const {
return mcontext.__gregs[REG_PC];
}
void ThreadInfo::FillCPUContext(RawContextCPU* out) const {
out->context_flags = MD_CONTEXT_RISCV64_FULL;
my_memcpy (out->iregs, mcontext.__gregs, MD_CONTEXT_RISCV64_GPR_COUNT * 8);
out->float_save.fcsr = mcontext.__fpregs.__d.__fcsr;
my_memcpy(&out->float_save.regs, &mcontext.__fpregs.__d.__f,
MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT * 8);
}
#endif // __riscv
void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) {
assert(gp_regs || size);
@ -279,6 +295,11 @@ void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) {
*gp_regs = mcontext.gregs;
if (size)
*size = sizeof(mcontext.gregs);
#elif defined(__riscv)
if (gp_regs)
*gp_regs = mcontext.__gregs;
if (size)
*size = sizeof(mcontext.__gregs);
#else
if (gp_regs)
*gp_regs = &regs;
@ -294,6 +315,11 @@ void ThreadInfo::GetFloatingPointRegisters(void** fp_regs, size_t* size) {
*fp_regs = &mcontext.fpregs;
if (size)
*size = sizeof(mcontext.fpregs);
#elif defined(__riscv)
if (fp_regs)
*fp_regs = &mcontext.__fpregs;
if (size)
*size = sizeof(mcontext.__fpregs);
#else
if (fp_regs)
*fp_regs = &fpregs;

2
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h vendored
View File

@ -68,7 +68,7 @@ struct ThreadInfo {
// Use the structures defined in <sys/user.h>
struct user_regs_struct regs;
struct user_fpsimd_struct fpregs;
#elif defined(__mips__)
#elif defined(__mips__) || defined(__riscv)
// Use the structure defined in <sys/ucontext.h>.
mcontext_t mcontext;
#endif

7
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc vendored
View File

@ -461,7 +461,7 @@ bool ExceptionHandler::HandleSignal(int /*sig*/, siginfo_t* info, void* uc) {
memcpy(&g_crash_context_.float_state, fp_ptr,
sizeof(g_crash_context_.float_state));
}
#elif !defined(__ARM_EABI__) && !defined(__mips__)
#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
// FP state is not part of user ABI on ARM Linux.
// In case of MIPS Linux FP state is already part of ucontext_t
// and 'float_state' is not a member of CrashContext.
@ -701,7 +701,7 @@ bool ExceptionHandler::WriteMinidump() {
}
#endif
#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv)
// FPU state is not part of ARM EABI ucontext_t.
memcpy(&context.float_state, context.context.uc_mcontext.fpregs,
sizeof(context.float_state));
@ -726,6 +726,9 @@ bool ExceptionHandler::WriteMinidump() {
#elif defined(__mips__)
context.siginfo.si_addr =
reinterpret_cast<void*>(context.context.uc_mcontext.pc);
#elif defined(__riscv)
context.siginfo.si_addr =
reinterpret_cast<void*>(context.context.uc_mcontext.__gregs[REG_PC]);
#else
#error "This code has not been ported to your platform yet."
#endif

2
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h vendored
View File

@ -192,7 +192,7 @@ class ExceptionHandler {
siginfo_t siginfo;
pid_t tid; // the crashing thread.
ucontext_t context;
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
// #ifdef this out because FP state is not part of user ABI for Linux ARM.
// In case of MIPS Linux FP state is already part of ucontext_t so
// 'float_state' is not required.

12
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc vendored
View File

@ -138,7 +138,7 @@ class MicrodumpWriter {
const MicrodumpExtraInfo& microdump_extra_info,
LinuxDumper* dumper)
: ucontext_(context ? &context->context : NULL),
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
float_state_(context ? &context->float_state : NULL),
#endif
dumper_(dumper),
@ -337,6 +337,12 @@ class MicrodumpWriter {
# else
# error "This mips ABI is currently not supported (n32)"
#endif
#elif defined(__riscv)
# if __riscv_xlen == 64
const char kArch[] = "riscv64";
# else
# error "This RISC-V ABI is currently not supported"
#endif
#else
#error "This code has not been ported to your platform yet"
#endif
@ -409,7 +415,7 @@ class MicrodumpWriter {
void DumpCPUState() {
RawContextCPU cpu;
my_memset(&cpu, 0, sizeof(RawContextCPU));
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
UContextReader::FillCPUContext(&cpu, ucontext_, float_state_);
#else
UContextReader::FillCPUContext(&cpu, ucontext_);
@ -605,7 +611,7 @@ class MicrodumpWriter {
void* Alloc(unsigned bytes) { return dumper_->allocator()->Alloc(bytes); }
const ucontext_t* const ucontext_;
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
const google_breakpad::fpstate_t* const float_state_;
#endif
LinuxDumper* dumper_;

5
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc vendored
View File

@ -112,6 +112,9 @@ bool LinuxCoreDumper::GetThreadInfoByIndex(size_t index, ThreadInfo* info) {
#elif defined(__mips__)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]);
#elif defined(__riscv)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]);
#else
#error "This code hasn't been ported to your platform yet."
#endif
@ -208,6 +211,8 @@ bool LinuxCoreDumper::EnumerateThreads() {
info.mcontext.mdlo = status->pr_reg[EF_LO];
info.mcontext.mdhi = status->pr_reg[EF_HI];
info.mcontext.pc = status->pr_reg[EF_CP0_EPC];
#elif defined(__riscv)
memcpy(info.mcontext.__gregs, status->pr_reg, sizeof(info.mcontext.__gregs));
#else // __mips__
memcpy(&info.regs, status->pr_reg, sizeof(info.regs));
#endif // __mips__

3
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h vendored
View File

@ -63,7 +63,8 @@ namespace google_breakpad {
(defined(__mips__) && _MIPS_SIM == _ABIO32)
typedef Elf32_auxv_t elf_aux_entry;
#elif defined(__x86_64) || defined(__aarch64__) || \
(defined(__mips__) && _MIPS_SIM != _ABIO32)
(defined(__mips__) && _MIPS_SIM != _ABIO32) || \
(defined(__riscv) && __riscv_xlen == 64)
typedef Elf64_auxv_t elf_aux_entry;
#endif

3
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc vendored
View File

@ -298,6 +298,9 @@ bool LinuxPtraceDumper::GetThreadInfoByIndex(size_t index, ThreadInfo* info) {
#elif defined(__mips__)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]);
#elif defined(__riscv)
stack_pointer =
reinterpret_cast<uint8_t*>(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]);
#else
#error "This code hasn't been ported to your platform yet."
#endif

14
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc vendored
View File

@ -136,7 +136,7 @@ class MinidumpWriter {
: fd_(minidump_fd),
path_(minidump_path),
ucontext_(context ? &context->context : NULL),
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
float_state_(context ? &context->float_state : NULL),
#endif
dumper_(dumper),
@ -468,7 +468,7 @@ class MinidumpWriter {
if (!cpu.Allocate())
return false;
my_memset(cpu.get(), 0, sizeof(RawContextCPU));
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
UContextReader::FillCPUContext(cpu.get(), ucontext_, float_state_);
#else
UContextReader::FillCPUContext(cpu.get(), ucontext_);
@ -897,7 +897,7 @@ class MinidumpWriter {
dirent->location.rva = 0;
}
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__)
#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || defined(__riscv)
bool WriteCPUInformation(MDRawSystemInfo* sys_info) {
char vendor_id[sizeof(sys_info->cpu.x86_cpu_info.vendor_id) + 1] = {0};
static const char vendor_id_name[] = "vendor_id";
@ -925,6 +925,12 @@ class MinidumpWriter {
# else
# error "This mips ABI is currently not supported (n32)"
#endif
#elif defined(__riscv)
# if __riscv_xlen == 64
MD_CPU_ARCHITECTURE_RISCV64;
# else
# error "This RISC-V ABI is currently not supported"
# endif
#elif defined(__i386__)
MD_CPU_ARCHITECTURE_X86;
#else
@ -1333,7 +1339,7 @@ class MinidumpWriter {
const char* path_; // Path to the file where the minidum should be written.
const ucontext_t* const ucontext_; // also from the signal handler
#if !defined(__ARM_EABI__) && !defined(__mips__)
#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
const google_breakpad::fpstate_t* const float_state_; // ditto
#endif
LinuxDumper* dumper_;

2
src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h vendored
View File

@ -48,7 +48,7 @@ class ExceptionHandler;
#if defined(__aarch64__)
typedef struct fpsimd_context fpstate_t;
#elif !defined(__ARM_EABI__) && !defined(__mips__)
#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv)
typedef std::remove_pointer<fpregset_t>::type fpstate_t;
#endif

62
src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S vendored
View File

@ -481,6 +481,68 @@ breakpad_getcontext:
.cfi_endproc
.size breakpad_getcontext, . - breakpad_getcontext
#elif defined(__riscv) && __riscv_xlen == 64
#define __NR_rt_sigprocmask 135
#define _NSIG8 64 / 8
#define SIG_BLOCK 0
.text
.global breakpad_getcontext
.hidden breakpad_getcontext
.type breakpad_getcontext, @function
.align 2
breakpad_getcontext:
sd ra, MCONTEXT_GREGS_OFFSET + 0*8(a0)
sd ra, MCONTEXT_GREGS_OFFSET + 1*8(a0)
sd sp, MCONTEXT_GREGS_OFFSET + 2*8(a0)
sd s0, MCONTEXT_GREGS_OFFSET + 8*8(a0)
sd s1, MCONTEXT_GREGS_OFFSET + 9*8(a0)
sd x0, MCONTEXT_GREGS_OFFSET + 10*8(a0) /* return 0 by overwriting a0. */
sd s2, MCONTEXT_GREGS_OFFSET + 18*8(a0)
sd s3, MCONTEXT_GREGS_OFFSET + 19*8(a0)
sd s4, MCONTEXT_GREGS_OFFSET + 20*8(a0)
sd s5, MCONTEXT_GREGS_OFFSET + 21*8(a0)
sd s6, MCONTEXT_GREGS_OFFSET + 22*8(a0)
sd s7, MCONTEXT_GREGS_OFFSET + 23*8(a0)
sd s8, MCONTEXT_GREGS_OFFSET + 24*8(a0)
sd s9, MCONTEXT_GREGS_OFFSET + 25*8(a0)
sd s10, MCONTEXT_GREGS_OFFSET + 26*8(a0)
sd s11, MCONTEXT_GREGS_OFFSET + 27*8(a0)
#ifndef __riscv_float_abi_soft
frsr a1
fsd fs0, MCONTEXT_FPREGS_OFFSET + 8*8(a0)
fsd fs1, MCONTEXT_FPREGS_OFFSET + 9*8(a0)
fsd fs2, MCONTEXT_FPREGS_OFFSET + 18*8(a0)
fsd fs3, MCONTEXT_FPREGS_OFFSET + 19*8(a0)
fsd fs4, MCONTEXT_FPREGS_OFFSET + 20*8(a0)
fsd fs5, MCONTEXT_FPREGS_OFFSET + 21*8(a0)
fsd fs6, MCONTEXT_FPREGS_OFFSET + 22*8(a0)
fsd fs7, MCONTEXT_FPREGS_OFFSET + 23*8(a0)
fsd fs8, MCONTEXT_FPREGS_OFFSET + 24*8(a0)
fsd fs9, MCONTEXT_FPREGS_OFFSET + 25*8(a0)
fsd fs10, MCONTEXT_FPREGS_OFFSET + 26*8(a0)
fsd fs11, MCONTEXT_FPREGS_OFFSET + 27*8(a0)
sw a1, MCONTEXT_FSR_OFFSET(a0)
#endif /* __riscv_float_abi_soft */
/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG / 8) */
li a3, _NSIG8
add a2, a0, UCONTEXT_SIGMASK_OFFSET
mv a1, zero
li a0, SIG_BLOCK
li a7, __NR_rt_sigprocmask
scall
/* Always return 0 for success, even if sigprocmask failed. */
mv a0, zero
ret
.size breakpad_getcontext, . - breakpad_getcontext
#else
#error "This file has not been ported for your CPU!"
#endif

3
src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc vendored
View File

@ -65,7 +65,8 @@ bool MemoryMappedFile::Map(const char* path, size_t offset) {
}
#if defined(__x86_64__) || defined(__aarch64__) || \
(defined(__mips__) && _MIPS_SIM == _ABI64)
(defined(__mips__) && _MIPS_SIM == _ABI64) || \
(defined(__riscv) && __riscv_xlen == 64)
struct kernel_stat st;
if (sys_fstat(fd, &st) == -1 || st.st_size < 0) {

8
src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h vendored
View File

@ -146,6 +146,14 @@
#endif
#define FPREGS_OFFSET_MXCSR 24
#elif defined(__riscv)
#define UCONTEXT_SIGMASK_OFFSET 40
#define MCONTEXT_GREGS_OFFSET 176
#define MCONTEXT_FPREGS_OFFSET 432
#define MCONTEXT_FSR_OFFSET (MCONTEXT_FPREGS_OFFSET + 32*8)
#else
#error "This header has not been ported for your CPU"
#endif

121
src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h vendored Normal file
View File

@ -0,0 +1,121 @@
/* Copyright 2013 Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google Inc. nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* minidump_format.h: A cross-platform reimplementation of minidump-related
* portions of DbgHelp.h from the Windows Platform SDK.
*
* (This is C99 source, please don't corrupt it with C++.)
*
* This file contains the necessary definitions to read minidump files
* produced on ARM. These files may be read on any platform provided
* that the alignments of these structures on the processing system are
* identical to the alignments of these structures on the producing system.
* For this reason, precise-sized types are used. The structures defined
* by this file have been laid out to minimize alignment problems by
* ensuring that all members are aligned on their natural boundaries.
* In some cases, tail-padding may be significant when different ABIs specify
* different tail-padding behaviors. To avoid problems when reading or
* writing affected structures, MD_*_SIZE macros are provided where needed,
* containing the useful size of the structures without padding.
*
* Structures that are defined by Microsoft to contain a zero-length array
* are instead defined here to contain an array with one element, as
* zero-length arrays are forbidden by standard C and C++. In these cases,
* *_minsize constants are provided to be used in place of sizeof. For a
* cleaner interface to these sizes when using C++, see minidump_size.h.
*
* These structures are also sufficient to populate minidump files.
*
* Because precise data type sizes are crucial for this implementation to
* function properly and portably, a set of primitive types with known sizes
* are used as the basis of each structure defined by this file.
*
* Author: Colin Blundell
*/
/*
* RISCV64 support
*/
#ifndef GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__
#define GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__
#include "google_breakpad/common/breakpad_types.h"
#define MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT 32
#define MD_CONTEXT_RISCV64_GPR_COUNT 32
typedef struct {
/* 32 64-bit floating point registers, f0 .. f31. */
uint64_t regs[MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT];
uint32_t fcsr; /* FPU control and status register */
} MDFloatingSaveAreaRISCV64;
/* For (MDRawContextRISCV64).context_flags. These values indicate the type of
* context stored in the structure. */
#define MD_CONTEXT_RISCV64 0x00400000
#define MD_CONTEXT_RISCV64_CONTROL (MD_CONTEXT_RISCV64 | 0x00000001)
#define MD_CONTEXT_RISCV64_INTEGER (MD_CONTEXT_RISCV64 | 0x00000002)
#define MD_CONTEXT_RISCV64_FLOATING_POINT (MD_CONTEXT_RISCV64 | 0x00000004)
#define MD_CONTEXT_RISCV64_DEBUG (MD_CONTEXT_RISCV64 | 0x00000008)
#define MD_CONTEXT_RISCV64_FULL (MD_CONTEXT_RISCV64_CONTROL | \
MD_CONTEXT_RISCV64_INTEGER | \
MD_CONTEXT_RISCV64_FLOATING_POINT)
#define MD_CONTEXT_RISCV64_ALL (MD_CONTEXT_RISCV64_FULL | MD_CONTEXT_RISCV64_DEBUG)
typedef struct {
/* Determines which fields of this struct are populated */
uint32_t context_flags;
/* 32 64-bit integer registers, x1 .. x31 + the PC
* Note the following fixed uses:
* x8 is the frame pointer
* x1 is the link register
* x2 is the stack pointer
* The PC is effectively x0.
*/
uint64_t iregs[MD_CONTEXT_RISCV64_GPR_COUNT];
/* The next field is included with MD_CONTEXT64_ARM_FLOATING_POINT */
MDFloatingSaveAreaRISCV64 float_save;
} MDRawContextRISCV64;
/* Indices into iregs for registers with a dedicated or conventional
* purpose.
*/
enum MDRISCV64RegisterNumbers {
MD_CONTEXT_RISCV64_REG_FP = 8,
MD_CONTEXT_RISCV64_REG_RA = 1,
MD_CONTEXT_RISCV64_REG_SP = 2,
MD_CONTEXT_RISCV64_REG_PC = 0
};
#endif /* GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ */

2
src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h vendored
View File

@ -118,6 +118,7 @@ typedef struct {
#include "minidump_cpu_mips.h"
#include "minidump_cpu_ppc.h"
#include "minidump_cpu_ppc64.h"
#include "minidump_cpu_riscv64.h"
#include "minidump_cpu_sparc.h"
#include "minidump_cpu_x86.h"
@ -660,6 +661,7 @@ typedef enum {
MD_CPU_ARCHITECTURE_PPC64 = 0x8002, /* Breakpad-defined value for PPC64 */
MD_CPU_ARCHITECTURE_ARM64_OLD = 0x8003, /* Breakpad-defined value for ARM64 */
MD_CPU_ARCHITECTURE_MIPS64 = 0x8004, /* Breakpad-defined value for MIPS64 */
MD_CPU_ARCHITECTURE_RISCV64 = 0x8005, /* Breakpad-defined value for RISCV64 */
MD_CPU_ARCHITECTURE_UNKNOWN = 0xffff /* PROCESSOR_ARCHITECTURE_UNKNOWN */
} MDCPUArchitecture;

35
src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context.h vendored
View File

@ -592,6 +592,41 @@ struct MinidumpContextMIPS64 {
uint64_t fir;
};
//! \brief 64bit RISC-V-specifc flags for MinidumpContextRISCV64::context_flags.
//! Based on minidump_cpu_riscv64.h from breakpad
enum MinidumpContextRISCV64Flags : uint32_t {
//! \brief Identifies the context structure as RISCV64.
kMinidumpContextRISCV64 = 0x00080000,
//! \brief Indicates the validity of integer registers.
//!
//! Registers `x1`-`x31` and pc are valid.
kMinidumpContextRISCV64Integer = kMinidumpContextRISCV64 | 0x00000002,
//! \brief Indicates the validity of floating point registers.
//!
//! Floating point registers `f0`-`f31`, and `fcsr` are valid
kMinidumpContextRISCV64FloatingPoint = kMinidumpContextRISCV64 | 0x00000004,
//! \brief Indicates the validity of all registers.
kMinidumpContextRISCV64All = kMinidumpContextRISCV64Integer |
kMinidumpContextRISCV64FloatingPoint,
};
//! \brief A 64bit RISCV CPU context (register state) carried in a minidump file.
struct MinidumpContextRISCV64 {
uint64_t context_flags;
//! \brief General purpose registers.
uint64_t regs[32];
//! \brief FPU registers.
uint64_t fpregs[32];
//! \brief FPU status register.
uint64_t fcsr;
};
} // namespace crashpad
#endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_

44
src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc vendored
View File

@ -101,6 +101,13 @@ MinidumpContextWriter::CreateFromSnapshot(const CPUContext* context_snapshot) {
break;
}
case kCPUArchitectureRISCV64: {
context = std::make_unique<MinidumpContextRISCV64Writer>();
reinterpret_cast<MinidumpContextRISCV64Writer*>(context.get())
->InitializeFromSnapshot(context_snapshot->riscv64);
break;
}
default: {
LOG(ERROR) << "unknown context architecture "
<< context_snapshot->architecture;
@ -453,4 +460,41 @@ size_t MinidumpContextMIPS64Writer::ContextSize() const {
return sizeof(context_);
}
MinidumpContextRISCV64Writer::MinidumpContextRISCV64Writer()
: MinidumpContextWriter(), context_() {
context_.context_flags = kMinidumpContextRISCV64;
}
MinidumpContextRISCV64Writer::~MinidumpContextRISCV64Writer() = default;
void MinidumpContextRISCV64Writer::InitializeFromSnapshot(
const CPUContextRISCV64* context_snapshot) {
DCHECK_EQ(state(), kStateMutable);
DCHECK_EQ(context_.context_flags, kMinidumpContextRISCV64);
context_.context_flags = kMinidumpContextRISCV64All;
static_assert(sizeof(context_.regs) == sizeof(context_snapshot->regs),
"GPRs size mismatch");
memcpy(context_.regs, context_snapshot->regs, sizeof(context_.regs));
static_assert(sizeof(context_.fpregs) == sizeof(context_snapshot->fpregs),
"FPRs size mismatch");
memcpy(context_.fpregs,
context_snapshot->fpregs,
sizeof(context_.fpregs));
context_.fcsr = context_snapshot->fcsr;
}
bool MinidumpContextRISCV64Writer::WriteObject(
FileWriterInterface* file_writer) {
DCHECK_EQ(state(), kStateWritable);
return file_writer->Write(&context_, sizeof(context_));
}
size_t MinidumpContextRISCV64Writer::ContextSize() const {
DCHECK_GE(state(), kStateFrozen);
return sizeof(context_);
}
} // namespace crashpad

40
src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h vendored
View File

@ -315,6 +315,46 @@ class MinidumpContextMIPS64Writer final : public MinidumpContextWriter {
DISALLOW_COPY_AND_ASSIGN(MinidumpContextMIPS64Writer);
};
//! \brief The writer for a MinidumpContextRISCV64 structure in a minidump file.
class MinidumpContextRISCV64Writer final : public MinidumpContextWriter {
public:
MinidumpContextRISCV64Writer();
~MinidumpContextRISCV64Writer() override;
//! \brief Initializes the MinidumpContextRISCV based on \a context_snapshot.
//!
//! \param[in] context_snapshot The context snapshot to use as source data.
//!
//! \note Valid in #kStateMutable. No mutation of context() may be done before
//! calling this method, and it is not normally necessary to alter
//! context() after calling this method.
void InitializeFromSnapshot(const CPUContextRISCV64* context_snapshot);
//! \brief Returns a pointer to the context structure that this object will
//! write.
//!
//! \attention This returns a non-`const` pointer to this object’s private
//! data so that a caller can populate the context structure directly.
//! This is done because providing setter interfaces to each field in the
//! context structure would be unwieldy and cumbersome. Care must be taken
//! to populate the context structure correctly. The context structure
//! must only be modified while this object is in the #kStateMutable
//! state.
MinidumpContextRISCV64* context() { return &context_; }
protected:
// MinidumpWritable:
bool WriteObject(FileWriterInterface* file_writer) override;
// MinidumpContextWriter:
size_t ContextSize() const override;
private:
MinidumpContextRISCV64 context_;
DISALLOW_COPY_AND_ASSIGN(MinidumpContextRISCV64Writer);
};
} // namespace crashpad
#endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_WRITER_H_

4
src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc vendored
View File

@ -135,6 +135,10 @@ std::string MinidumpMiscInfoDebugBuildString() {
static constexpr char kCPU[] = "mips";
#elif defined(ARCH_CPU_MIPS64EL)
static constexpr char kCPU[] = "mips64";
#elif defined(ARCH_CPU_RISCV)
static constexpr char kCPU[] = "riscv";
#elif defined(ARCH_CPU_RISCV64)
static constexpr char kCPU[] = "riscv64";
#else
#error define kCPU for this CPU
#endif

10
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc vendored
View File

@ -112,6 +112,16 @@ void CaptureMemory::PointedToByContext(const CPUContext& context,
for (size_t i = 0; i < base::size(context.mipsel->regs); ++i) {
MaybeCaptureMemoryAround(delegate, context.mipsel->regs[i]);
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
if (context.architecture == kCPUArchitectureRISCV) {
for (size_t i = 0; i < base::size(context.riscv->regs); ++i) {
MaybeCaptureMemoryAround(delegate, context.riscv->regs[i]);
}
} else {
for (size_t i = 0; i < base::size(context.riscv64->regs); ++i) {
MaybeCaptureMemoryAround(delegate, context.riscv64->regs[i]);
}
}
#else
#error Port.
#endif

8
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h vendored
View File

@ -43,7 +43,13 @@ enum CPUArchitecture {
kCPUArchitectureMIPSEL,
//! \brief 64-bit MIPSEL.
kCPUArchitectureMIPS64EL
kCPUArchitectureMIPS64EL,
//! \brief 32-bit RISCV.
kCPUArchitectureRISCV,
//! \brief 64-bit RISCV.
kCPUArchitectureRISCV64
};
} // namespace crashpad

2
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc vendored
View File

@ -196,10 +196,12 @@ bool CPUContext::Is64Bit() const {
case kCPUArchitectureX86_64:
case kCPUArchitectureARM64:
case kCPUArchitectureMIPS64EL:
case kCPUArchitectureRISCV64:
return true;
case kCPUArchitectureX86:
case kCPUArchitectureARM:
case kCPUArchitectureMIPSEL:
case kCPUArchitectureRISCV:
return false;
default:
NOTREACHED();

16
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h vendored
View File

@ -352,6 +352,20 @@ struct CPUContextMIPS64 {
uint64_t fir;
};
//! \brief A context structure carrying RISC CPU state.
struct CPUContextRISCV {
uint32_t regs[32];
uint64_t fpregs[32];
uint32_t fcsr;
};
//! \brief A context structure carrying RISC64 CPU state.
struct CPUContextRISCV64 {
uint64_t regs[32];
uint64_t fpregs[32];
uint32_t fcsr;
};
//! \brief A context structure capable of carrying the context of any supported
//! CPU architecture.
struct CPUContext {
@ -382,6 +396,8 @@ struct CPUContext {
CPUContextARM64* arm64;
CPUContextMIPS* mipsel;
CPUContextMIPS64* mips64;
CPUContextRISCV* riscv;
CPUContextRISCV64* riscv64;
};
};

24
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc vendored
View File

@ -266,6 +266,30 @@ void InitializeCPUContextARM64_OnlyFPSIMD(
context->fpcr = float_context.fpcr;
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
template <typename Traits>
void InitializeCPUContextRISCV(
const typename Traits::SignalThreadContext& thread_context,
const typename Traits::SignalFloatContext& float_context,
typename Traits::CPUContext* context) {
static_assert(sizeof(context->regs) == sizeof(thread_context),
"registers size mismatch");
static_assert(sizeof(context->fpregs) == sizeof(float_context.f),
"fp registers size mismatch");
memcpy(&context->regs, &thread_context, sizeof(context->regs));
memcpy(&context->fpregs, &float_context, sizeof(context->fpregs));
context->fcsr = float_context.fcsr;
}
template void InitializeCPUContextRISCV<ContextTraits32>(
const ContextTraits32::SignalThreadContext& thread_context,
const ContextTraits32::SignalFloatContext& float_context,
ContextTraits32::CPUContext* context);
template void InitializeCPUContextRISCV<ContextTraits64>(
const ContextTraits64::SignalThreadContext& thread_context,
const ContextTraits64::SignalFloatContext& float_context,
ContextTraits64::CPUContext* context);
#endif // ARCH_CPU_X86_FAMILY
} // namespace internal

16
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h vendored
View File

@ -174,6 +174,22 @@ void InitializeCPUContextMIPS(
#endif // ARCH_CPU_MIPS_FAMILY || DOXYGEN
#if defined(ARCH_CPU_RISCV_FAMILY) || DOXYGEN
//! \brief Initializes a CPUContextRISCV structure from native context
//! structures on Linux.
//!
//! \param[in] thread_context The native thread context.
//! \param[in] float_context The native float context.
//! \param[out] context The CPUContextRISCV structure to initialize.
template <typename Traits>
void InitializeCPUContextRISCV(
const typename Traits::SignalThreadContext& thread_context,
const typename Traits::SignalFloatContext& float_context,
typename Traits::CPUContext* context);
#endif // ARCH_CPU_RISCV_FAMILY || DOXYGEN
} // namespace internal
} // namespace crashpad

55
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc vendored
View File

@ -323,6 +323,61 @@ bool ExceptionSnapshotLinux::ReadContext<ContextTraits64>(
reader, context_address, context_.mips64);
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
template <typename Traits>
static bool ReadContext(ProcessReaderLinux* reader,
LinuxVMAddress context_address,
typename Traits::CPUContext* dest_context) {
const ProcessMemory* memory = reader->Memory();
LinuxVMAddress gregs_address = context_address +
offsetof(UContext<Traits>, mcontext) +
offsetof(typename Traits::MContext, gregs);
typename Traits::SignalThreadContext thread_context;
if (!memory->Read(gregs_address, sizeof(thread_context), &thread_context)) {
LOG(ERROR) << "Couldn't read gregs";
return false;
}
LinuxVMAddress fpregs_address = context_address +
offsetof(UContext<Traits>, mcontext) +
offsetof(typename Traits::MContext, fpregs);
typename Traits::SignalFloatContext fp_context;
if (!memory->Read(fpregs_address, sizeof(fp_context), &fp_context)) {
LOG(ERROR) << "Couldn't read fpregs";
return false;
}
InitializeCPUContextRISCV<Traits>(thread_context, fp_context, dest_context);
return true;
}
template <>
bool ExceptionSnapshotLinux::ReadContext<ContextTraits32>(
ProcessReaderLinux* reader,
LinuxVMAddress context_address) {
context_.architecture = kCPUArchitectureRISCV;
context_.riscv = &context_union_.riscv;
return internal::ReadContext<ContextTraits32>(
reader, context_address, context_.riscv);
}
template <>
bool ExceptionSnapshotLinux::ReadContext<ContextTraits64>(
ProcessReaderLinux* reader,
LinuxVMAddress context_address) {
context_.architecture = kCPUArchitectureRISCV64;
context_.riscv64 = &context_union_.riscv64;
return internal::ReadContext<ContextTraits64>(
reader, context_address, context_.riscv64);
}
#endif // ARCH_CPU_X86_FAMILY
bool ExceptionSnapshotLinux::Initialize(ProcessReaderLinux* process_reader,

3
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h vendored
View File

@ -84,6 +84,9 @@ class ExceptionSnapshotLinux final : public ExceptionSnapshot {
#elif defined(ARCH_CPU_MIPS_FAMILY)
CPUContextMIPS mipsel;
CPUContextMIPS64 mips64;
#elif defined(ARCH_CPU_RISCV_FAMILY)
CPUContextRISCV riscv;
CPUContextRISCV64 riscv64;
#endif
} context_union_;
CPUContext context_;

3
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc vendored
View File

@ -108,6 +108,9 @@ void ProcessReaderLinux::Thread::InitializeStack(ProcessReaderLinux* reader) {
#elif defined(ARCH_CPU_MIPS_FAMILY)
stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.regs[29]
: thread_info.thread_context.t32.regs[29];
#elif defined(ARCH_CPU_RISCV_FAMILY)
stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.sp
: thread_info.thread_context.t32.sp;
#else
#error Port.
#endif

61
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h vendored
View File

@ -422,6 +422,67 @@ static_assert(offsetof(UContext<ContextTraits64>, mcontext.fpregs) ==
"context offset mismatch");
#endif
#elif defined(ARCH_CPU_RISCV_FAMILY)
struct MContext32 {
uint32_t gregs[32];
uint64_t fpregs[32];
unsigned int fcsr;
};
struct MContext64 {
uint64_t gregs[32];
uint64_t fpregs[32];
unsigned int fcsr;
};
struct ContextTraits32 : public Traits32 {
using MContext = MContext32;
using SignalThreadContext = ThreadContext::t32_t;
using SignalFloatContext = FloatContext::f32_t;
using CPUContext = CPUContextRISCV;
};
struct ContextTraits64 : public Traits64 {
using MContext = MContext64;
using SignalThreadContext = ThreadContext::t64_t;
using SignalFloatContext = FloatContext::f64_t;
using CPUContext = CPUContextRISCV64;
};
template <typename Traits>
struct UContext {
typename Traits::ULong flags;
typename Traits::Address link;
SignalStack<Traits> stack;
Sigset<Traits> sigmask;
char padding[128 - sizeof(sigmask)];
typename Traits::Char_64Only padding2[8];
typename Traits::MContext mcontext;
};
#if defined(ARCH_CPU_RISCV)
static_assert(offsetof(UContext<ContextTraits32>, mcontext) ==
offsetof(ucontext_t, uc_mcontext),
"context offset mismatch");
static_assert(offsetof(UContext<ContextTraits32>, mcontext.gregs) ==
offsetof(ucontext_t, uc_mcontext.__gregs),
"context offset mismatch");
static_assert(offsetof(UContext<ContextTraits32>, mcontext.fpregs) ==
offsetof(ucontext_t, uc_mcontext.__fpregs),
"context offset mismatch");
#elif defined(ARCH_CPU_RISCV64)
static_assert(offsetof(UContext<ContextTraits64>, mcontext) ==
offsetof(ucontext_t, uc_mcontext),
"context offset mismatch");
static_assert(offsetof(UContext<ContextTraits64>, mcontext.gregs) ==
offsetof(ucontext_t, uc_mcontext.__gregs),
"context offset mismatch");
static_assert(offsetof(UContext<ContextTraits64>, mcontext.fpregs) ==
offsetof(ucontext_t, uc_mcontext.__fpregs),
"context offset mismatch");
#endif
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY

12
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc vendored
View File

@ -204,6 +204,9 @@ CPUArchitecture SystemSnapshotLinux::GetCPUArchitecture() const {
#elif defined(ARCH_CPU_MIPS_FAMILY)
return process_reader_->Is64Bit() ? kCPUArchitectureMIPS64EL
: kCPUArchitectureMIPSEL;
#elif defined(ARCH_CPU_RISCV_FAMILY)
return process_reader_->Is64Bit() ? kCPUArchitectureRISCV64
: kCPUArchitectureRISCV;
#else
#error port to your architecture
#endif
@ -219,6 +222,9 @@ uint32_t SystemSnapshotLinux::CPURevision() const {
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return 0;
#elif defined(ARCH_CPU_RISCV_FAMILY)
// Not implementable on RISCV
return 0;
#else
#error port to your architecture
#endif
@ -239,6 +245,9 @@ std::string SystemSnapshotLinux::CPUVendor() const {
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return std::string();
#elif defined(ARCH_CPU_RISCV_FAMILY)
// Not implementable on RISCV
return std::string();
#else
#error port to your architecture
#endif
@ -372,6 +381,9 @@ bool SystemSnapshotLinux::NXEnabled() const {
#elif defined(ARCH_CPU_MIPS_FAMILY)
// Not implementable on MIPS
return false;
#elif defined(ARCH_CPU_RISCV_FAMILY)
// Not implementable on RISCV
return false;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY

16
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc vendored
View File

@ -186,6 +186,22 @@ bool ThreadSnapshotLinux::Initialize(ProcessReaderLinux* process_reader,
thread.thread_info.float_context.f32,
context_.mipsel);
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
if (process_reader->Is64Bit()) {
context_.architecture = kCPUArchitectureRISCV64;
context_.riscv64 = &context_union_.riscv64;
InitializeCPUContextRISCV<ContextTraits64>(
thread.thread_info.thread_context.t64,
thread.thread_info.float_context.f64,
context_.riscv64);
} else {
context_.architecture = kCPUArchitectureRISCV;
context_.riscv = &context_union_.riscv;
InitializeCPUContextRISCV<ContextTraits32>(
thread.thread_info.thread_context.t32,
thread.thread_info.float_context.f32,
context_.riscv);
}
#else
#error Port.
#endif

3
src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h vendored
View File

@ -68,6 +68,9 @@ class ThreadSnapshotLinux final : public ThreadSnapshot {
#elif defined(ARCH_CPU_MIPS_FAMILY)
CPUContextMIPS mipsel;
CPUContextMIPS64 mips64;
#elif defined(ARCH_CPU_RISCV_FAMILY)
CPUContextRISCV riscv;
CPUContextRISCV64 riscv64;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY

90
src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc vendored
View File

@ -398,6 +398,96 @@ bool GetThreadArea64(pid_t tid,
return true;
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
template <typename Destination>
bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) {
iovec iov;
iov.iov_base = dest;
iov.iov_len = sizeof(*dest);
if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast<void*>(set), &iov) != 0) {
PLOG_IF(ERROR, can_log) << "ptrace";
return false;
}
if (iov.iov_len != sizeof(*dest)) {
LOG_IF(ERROR, can_log) << "Unexpected registers size";
return false;
}
return true;
}
bool GetFloatingPointRegisters32(pid_t tid,
FloatContext* context,
bool can_log) {
return false;
}
bool GetFloatingPointRegisters64(pid_t tid,
FloatContext* context,
bool can_log) {
return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log);
}
bool GetThreadArea32(pid_t tid,
const ThreadContext& context,
LinuxVMAddress* address,
bool can_log) {
return false;
}
bool GetThreadArea64(pid_t tid,
const ThreadContext& context,
LinuxVMAddress* address,
bool can_log) {
*address = context.t64.tp;
return true;
}
#elif defined(ARCH_CPU_RISCV_FAMILY)
template <typename Destination>
bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) {
iovec iov;
iov.iov_base = dest;
iov.iov_len = sizeof(*dest);
if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast<void*>(set), &iov) != 0) {
PLOG_IF(ERROR, can_log) << "ptrace";
return false;
}
if (iov.iov_len != sizeof(*dest)) {
LOG_IF(ERROR, can_log) << "Unexpected registers size";
return false;
}
return true;
}
bool GetFloatingPointRegisters32(pid_t tid,
FloatContext* context,
bool can_log) {
return false;
}
bool GetFloatingPointRegisters64(pid_t tid,
FloatContext* context,
bool can_log) {
return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log);
}
bool GetThreadArea32(pid_t tid,
const ThreadContext& context,
LinuxVMAddress* address,
bool can_log) {
return false;
}
bool GetThreadArea64(pid_t tid,
const ThreadContext& context,
LinuxVMAddress* address,
bool can_log) {
*address = context.t64.tp;
return true;
}
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY

78
src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h vendored
View File

@ -79,6 +79,40 @@ union ThreadContext {
uint32_t cp0_status;
uint32_t cp0_cause;
uint32_t padding1_;
#elif defined(ARCH_CPU_RISCV_FAMILY)
// Reflects user_regs_struct in asm/ptrace.h.
uint32_t pc;
uint32_t ra;
uint32_t sp;
uint32_t gp;
uint32_t tp;
uint32_t t0;
uint32_t t1;
uint32_t t2;
uint32_t s0;
uint32_t s1;
uint32_t a0;
uint32_t a1;
uint32_t a2;
uint32_t a3;
uint32_t a4;
uint32_t a5;
uint32_t a6;
uint32_t a7;
uint32_t s2;
uint32_t s3;
uint32_t s4;
uint32_t s5;
uint32_t s6;
uint32_t s7;
uint32_t s8;
uint32_t s9;
uint32_t s10;
uint32_t s11;
uint32_t t3;
uint32_t t4;
uint32_t t5;
uint32_t t6;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@ -132,6 +166,40 @@ union ThreadContext {
uint64_t cp0_badvaddr;
uint64_t cp0_status;
uint64_t cp0_cause;
#elif defined(ARCH_CPU_RISCV_FAMILY)
// Reflects user_regs_struct in asm/ptrace.h.
uint64_t pc;
uint64_t ra;
uint64_t sp;
uint64_t gp;
uint64_t tp;
uint64_t t0;
uint64_t t1;
uint64_t t2;
uint64_t s0;
uint64_t s1;
uint64_t a0;
uint64_t a1;
uint64_t a2;
uint64_t a3;
uint64_t a4;
uint64_t a5;
uint64_t a6;
uint64_t a7;
uint64_t s2;
uint64_t s3;
uint64_t s4;
uint64_t s5;
uint64_t s6;
uint64_t s7;
uint64_t s8;
uint64_t s9;
uint64_t s10;
uint64_t s11;
uint64_t t3;
uint64_t t4;
uint64_t t5;
uint64_t t6;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@ -143,11 +211,12 @@ union ThreadContext {
using NativeThreadContext = user_regs;
#elif defined(ARCH_CPU_MIPS_FAMILY)
// No appropriate NativeThreadsContext type available for MIPS
#elif defined(ARCH_CPU_RISCV_FAMILY)
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64
#if !defined(ARCH_CPU_MIPS_FAMILY)
#if !defined(ARCH_CPU_MIPS_FAMILY) && !defined(ARCH_CPU_RISCV_FAMILY)
#if defined(ARCH_CPU_32_BITS)
static_assert(sizeof(t32_t) == sizeof(NativeThreadContext), "Size mismatch");
#else // ARCH_CPU_64_BITS
@ -218,6 +287,9 @@ union FloatContext {
} fpregs[32];
uint32_t fpcsr;
uint32_t fpu_id;
#elif defined(ARCH_CPU_RISCV_FAMILY)
uint64_t f[32];
uint32_t fcsr;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@ -252,6 +324,9 @@ union FloatContext {
double fpregs[32];
uint32_t fpcsr;
uint32_t fpu_id;
#elif defined(ARCH_CPU_RISCV_FAMILY)
uint64_t f[32];
uint32_t fcsr;
#else
#error Port.
#endif // ARCH_CPU_X86_FAMILY
@ -280,6 +355,7 @@ union FloatContext {
static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch");
#elif defined(ARCH_CPU_MIPS_FAMILY)
// No appropriate floating point context native type for available MIPS.
#elif defined(ARCH_CPU_RISCV_FAMILY)
#else
#error Port.
#endif // ARCH_CPU_X86

38
src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h vendored Normal file
View File

@ -0,0 +1,38 @@
/*
* Autogenerated by the Meson build system.
* Do not edit, your changes will be lost.
*/
#pragma once
#define ARCH_AARCH64 0
#define ARCH_ARM 0
#define ARCH_PPC64LE 0
#define ARCH_X86 0
#define ARCH_X86_32 0
#define ARCH_X86_64 0
#define CONFIG_16BPC 1
#define CONFIG_8BPC 1
// #define CONFIG_LOG 1 -- Logging is controlled by Chromium
#define ENDIANNESS_BIG 0
#define HAVE_ASM 0
#define HAVE_AS_FUNC 0
#define HAVE_CLOCK_GETTIME 1
#define HAVE_GETAUXVAL 1
#define HAVE_POSIX_MEMALIGN 1
#define HAVE_UNISTD_H 1

132
src/3rdparty/chromium/third_party/lss/linux_syscall_support.h vendored
View File

@ -88,7 +88,7 @@
*/
#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) || \
defined(__mips__) || defined(__PPC__) || defined(__ARM_EABI__) || \
defined(__aarch64__) || defined(__s390__)) \
defined(__aarch64__) || defined(__s390__) || defined(__riscv)) \
&& (defined(__linux) || defined(__ANDROID__))
#ifndef SYS_CPLUSPLUS
@ -301,7 +301,7 @@ struct kernel_old_sigaction {
} __attribute__((packed,aligned(4)));
#elif (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32)
#define kernel_old_sigaction kernel_sigaction
#elif defined(__aarch64__)
#elif defined(__aarch64__) || defined(__riscv)
// No kernel_old_sigaction defined for arm64.
#endif
@ -341,7 +341,9 @@ struct kernel_sigaction {
void (*sa_sigaction_)(int, siginfo_t *, void *);
};
unsigned long sa_flags;
#ifndef __riscv
void (*sa_restorer)(void);
#endif
struct kernel_sigset_t sa_mask;
#endif
};
@ -519,7 +521,7 @@ struct kernel_stat {
int st_blocks;
int st_pad4[14];
};
#elif defined(__aarch64__)
#elif defined(__aarch64__) || defined(__riscv)
struct kernel_stat {
unsigned long st_dev;
unsigned long st_ino;
@ -1065,7 +1067,7 @@ struct kernel_statfs {
#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
#endif
/* End of ARM 3/EABI definitions */
#elif defined(__aarch64__)
#elif defined(__aarch64__) || defined(__riscv)
#ifndef __NR_setxattr
#define __NR_setxattr 5
#endif
@ -1880,7 +1882,7 @@ struct kernel_statfs {
#undef LSS_RETURN
#if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) \
|| defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__))
|| defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__) || defined(__riscv))
/* Failing system calls return a negative result in the range of
* -1..-4095. These are "errno" values with the sign inverted.
*/
@ -3373,6 +3375,122 @@ struct kernel_statfs {
}
LSS_RETURN(int, __ret);
}
#elif defined(__riscv)
#undef LSS_REG
#define LSS_REG(r,a) register int64_t __r##r __asm__("a"#r) = (int64_t)a
#undef LSS_BODY
#define LSS_BODY(type,name,args...) \
register int64_t __res_a0 __asm__("a0"); \
register int64_t __a7 __asm__("a7") = __NR_##name; \
int64_t __res; \
__asm__ __volatile__ ("scall\n" \
: "=r"(__res_a0) \
: "r"(__a7) , ## args \
: "memory"); \
__res = __res_a0; \
LSS_RETURN(type, __res)
#undef _syscall0
#define _syscall0(type, name) \
type LSS_NAME(name)(void) { \
LSS_BODY(type, name); \
}
#undef _syscall1
#define _syscall1(type, name, type1, arg1) \
type LSS_NAME(name)(type1 arg1) { \
LSS_REG(0, arg1); LSS_BODY(type, name, "r"(__r0)); \
}
#undef _syscall2
#define _syscall2(type, name, type1, arg1, type2, arg2) \
type LSS_NAME(name)(type1 arg1, type2 arg2) { \
LSS_REG(0, arg1); LSS_REG(1, arg2); \
LSS_BODY(type, name, "r"(__r0), "r"(__r1)); \
}
#undef _syscall3
#define _syscall3(type, name, type1, arg1, type2, arg2, type3, arg3) \
type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3) { \
LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2)); \
}
#undef _syscall4
#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
LSS_REG(3, arg4); \
LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3)); \
}
#undef _syscall5
#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
type5,arg5) \
type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
type5 arg5) { \
LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
LSS_REG(3, arg4); LSS_REG(4, arg5); \
LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
"r"(__r4)); \
}
#undef _syscall6
#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
type5,arg5,type6,arg6) \
type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
type5 arg5, type6 arg6) { \
LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \
LSS_REG(3, arg4); LSS_REG(4, arg5); LSS_REG(5, arg6); \
LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \
"r"(__r4), "r"(__r5)); \
}
LSS_INLINE int LSS_NAME(clone)(int (*fn)(void *), void *child_stack,
int flags, void *arg, int *parent_tidptr,
void *newtls, int *child_tidptr) {
int64_t __res;
{
register int64_t __res_a0 __asm__("a0");
register uint64_t __flags __asm__("a0") = flags;
register void *__stack __asm__("a1") = child_stack;
register void *__ptid __asm__("a2") = parent_tidptr;
register void *__tls __asm__("a3") = newtls;
register int *__ctid __asm__("a4") = child_tidptr;
__asm__ __volatile__(/* Push "arg" and "fn" onto the stack that will be
* used by the child.
*/
"addi %2,%2,-16\n"
"sd %1, 0(%2)\n"
"sd %4, 8(%2)\n"
/* %a0 = syscall(%a0 = flags,
* %a1 = child_stack,
* %a2 = parent_tidptr,
* %a3 = newtls,
* %a4 = child_tidptr)
*/
"li a7, %8\n"
"scall\n"
/* if (%a0 != 0)
* return %a0;
*/
"bnez %0, 1f\n"
/* In the child, now. Call "fn(arg)".
*/
"ld a1, 0(sp)\n"
"ld a0, 8(sp)\n"
"jalr a1\n"
/* Call _exit(%a0).
*/
"li a7, %9\n"
"scall\n"
"1:\n"
: "=r" (__res_a0)
: "r"(fn), "r"(__stack), "r"(__flags), "r"(arg),
"r"(__ptid), "r"(__tls), "r"(__ctid),
"i"(__NR_clone), "i"(__NR_exit)
: "cc", "memory");
__res = __res_a0;
}
LSS_RETURN(int, __res);
}
#endif
#define __NR__exit __NR_exit
#define __NR__gettid __NR_gettid
@ -4181,7 +4299,7 @@ struct kernel_statfs {
LSS_SC_BODY(4, int, 8, d, type, protocol, sv);
}
#endif
#if defined(__ARM_EABI__) || defined (__aarch64__)
#if defined(__ARM_EABI__) || defined (__aarch64__) || defined(__riscv)
LSS_INLINE _syscall3(ssize_t, recvmsg, int, s, struct kernel_msghdr*, msg,
int, flags)
LSS_INLINE _syscall3(ssize_t, sendmsg, int, s, const struct kernel_msghdr*,
@ -4503,7 +4621,7 @@ struct kernel_statfs {
// TODO: define this in an arch-independant way instead of inlining the clone
// syscall body.
# if defined(__aarch64__)
# if defined(__aarch64__) || defined(__riscv)
LSS_INLINE pid_t LSS_NAME(fork)(void) {
// No fork syscall on aarch64 - implement by means of the clone syscall.
// Note that this does not reset glibc's cached view of the PID/TID, so

1
src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn vendored
View File

@ -149,6 +149,7 @@ swiftshader_llvm_source_set("swiftshader_llvm") {
deps += [ ":swiftshader_llvm_ppc" ]
} else if (current_cpu == "x86" || current_cpu == "x64") {
deps += [ ":swiftshader_llvm_x86" ]
} else if (current_cpu == "riscv64") {
} else {
assert(false, "Unsupported current_cpu")
}

2
src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc vendored
View File

@ -30,7 +30,7 @@ bool VectorDifference(const uint8_t* image1, const uint8_t* image2) {
static bool (*diff_proc)(const uint8_t*, const uint8_t*) = nullptr;
if (!diff_proc) {
#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY)
#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) || defined(WEBRTC_ARCH_RISCV_FAMILY)
// For ARM and MIPS processors, always use C version.
// TODO(hclam): Implement a NEON version.
diff_proc = &VectorDifference_C;

4
src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h vendored
View File

@ -50,6 +50,10 @@
#elif defined(__EMSCRIPTEN__)
#define WEBRTC_ARCH_32_BITS
#define WEBRTC_ARCH_LITTLE_ENDIAN
#elif defined(__riscv) && __riscv_xlen == 64
#define WEBRTC_ARCH_RISCV_FAMILY
#define WEBRTC_ARCH_64_BITS
#define WEBRTC_ARCH_LITTLE_ENDIAN
#else
#error Please add support for your architecture in rtc_base/system/arch.h
#endif

3
src/3rdparty/gn/tools/gn/args.cc vendored
View File

@ -329,6 +329,7 @@ void Args::SetSystemVarsLocked(Scope* dest) const {
static const char kMips64[] = "mips64el";
static const char kS390X[] = "s390x";
static const char kPPC64[] = "ppc64";
static const char kRiscv64[] = "riscv64";
const char* arch = nullptr;
// Set the host CPU architecture based on the underlying OS, not
@ -353,6 +354,8 @@ void Args::SetSystemVarsLocked(Scope* dest) const {
// This allows us to use the same toolchain as ppc64 BE
// and specific flags are included using the host_byteorder logic.
arch = kPPC64;
else if (os_arch == "riscv64")
arch = kRiscv64;
else
CHECK(false) << "OS architecture not handled. (" << os_arch << ")";

10
src/3rdparty/gn/util/build_config.h vendored
View File

@ -172,6 +172,16 @@
#define ARCH_CPU_32_BITS 1
#define ARCH_CPU_BIG_ENDIAN 1
#endif
#elif defined(__riscv)
#define ARCH_CPU_RISCV_FAMILY 1
#if __riscv_xlen == 64
#define ARCH_CPU_RISCV64 1
#define ARCH_CPU_64_BITS 1
#else
#define ARCH_CPU_RISCV32 1
#define ARCH_CPU_32_BITS 1
#endif
#define ARCH_CPU_LITTLE_ENDIAN 1
#else
#error Please add support for your architecture in build_config.h
#endif