commit
656b2bbdaf
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@ -13,7 +13,10 @@ from .base_engine import BaseEngine, Response
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if is_vllm_available():
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if is_vllm_available():
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from vllm import AsyncEngineArgs, AsyncLLMEngine, RequestOutput, SamplingParams
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from vllm import AsyncEngineArgs, AsyncLLMEngine, RequestOutput, SamplingParams
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from vllm.lora.request import LoRARequest
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from vllm.lora.request import LoRARequest
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from vllm.sequence import MultiModalData
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try:
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from vllm.multimodal import MultiModalData # vllm==0.5.0
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except ImportError:
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from vllm.sequence import MultiModalData # vllm<0.5.0
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if TYPE_CHECKING:
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if TYPE_CHECKING:
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