404 lines
9.9 KiB
ArmAsm
404 lines
9.9 KiB
ArmAsm
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///******************************************************************************
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// *
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// * Copyright (C) 2018 The Android Open Source Project
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// *
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// * Licensed under the Apache License, Version 2.0 (the "License");
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// * you may not use this file except in compliance with the License.
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// * You may obtain a copy of the License at:
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// *
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// * http://www.apache.org/licenses/LICENSE-2.0
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// *
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// * Unless required by applicable law or agreed to in writing, software
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// * distributed under the License is distributed on an "AS IS" BASIS,
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// * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// * See the License for the specific language governing permissions and
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// * limitations under the License.
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// *
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// *****************************************************************************
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// * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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//*/
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.macro push_v_regs
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stp q8, q9, [sp, #-32]!
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stp q10, q11, [sp, #-32]!
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stp q12, q13, [sp, #-32]!
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stp q14, q15, [sp, #-32]!
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stp x21, x22, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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.endm
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.macro pop_v_regs
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ldp x23, x24, [sp], #16
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ldp x21, x22, [sp], #16
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ldp q14, q15, [sp], #32
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ldp q12, q13, [sp], #32
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ldp q10, q11, [sp], #32
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ldp q8, q9, [sp], #32
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.endm
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.macro swp reg1, reg2
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MOV X16, \reg1
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MOV \reg1, \reg2
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MOV \reg2, x16
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.endm
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.text
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.global ixheaacd_sbr_qmfsyn64_winadd
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ixheaacd_sbr_qmfsyn64_winadd:
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push_v_regs
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MOV w7, #0x8000
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LD1 {v0.4h}, [x0], #8
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MOV x12, x2
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dup v30.4s, w7
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LD1 {v1.4h}, [x2], #8
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dup v22.4s, w4
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MOV x10, x0
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MOV x11, x2
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ADD x0, x0, #504
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ADD x2, x2, #248
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NEG v28.4s, v22.4s
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sshL v20.4s, v30.4s, v28.4s
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MOV x6, #64
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LSL x6, x6, #1
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ADD x12, x12, x6
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MOV x7, #128
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LSL x9, x7, #1
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ADD x1, x1, x9
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MOV x6, #16
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MOV x7, #128
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LSL x9, x7, #1
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MOV x7, #256
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LSL x8, x7, #1
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LSL x5, x5, #1
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LD1 {v2.4h}, [x0], x8
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mov v26.16b, v20.16b
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sMLAL v26.4s, v0.4h, v1.4h
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LD1 {v3.4h}, [x2], x9
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LD1 {v4.4h}, [x0], x8
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sMLAL v26.4s, v2.4h, v3.4h
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LD1 {v5.4h}, [x2], x9
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LD1 {v6.4h}, [x0], x8
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sMLAL v26.4s, v5.4h, v4.4h
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LD1 {v7.4h}, [x2], x9
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LD1 {v8.4h}, [x0], x8
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sMLAL v26.4s, v7.4h, v6.4h
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LD1 {v9.4h}, [x2], x9
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MOV x0, x10
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MOV x2, x11
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LD1 {v10.4h}, [x1], #8
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sMLAL v26.4s, v9.4h, v8.4h
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MOV x10, x1
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LD1 {v11.4h}, [x12], #8
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ADD x1, x1, #504
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MOV x11, x12
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LD1 {v12.4h}, [x1], x8
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ADD x12, x12, #248
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sMLAL v26.4s, v10.4h, v11.4h
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LD1 {v13.4h}, [x12], x9
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LD1 {v14.4h}, [x1], x8
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sMLAL v26.4s, v12.4h, v13.4h
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LD1 {v15.4h}, [x12], x9
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LD1 {v16.4h}, [x1], x8
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sMLAL v26.4s, v15.4h, v14.4h
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LD1 {v17.4h}, [x12], x9
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LD1 {v18.4h}, [x1], x8
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sMLAL v26.4s, v17.4h, v16.4h
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LD1 {v19.4h}, [x12], x9
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sMLAL v26.4s, v19.4h, v18.4h
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LD1 {v0.4h}, [x0], #8
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MOV x12, x11
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MOV x1, x10
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LD1 {v1.4h}, [x2], #8
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MOV x10, x0
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sQshL v26.4s, v26.4s, v22.4s
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ADD x0, x0, #504
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MOV x11, x2
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LD1 {v2.4h}, [x0], x8
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ADD x2, x2, #248
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sshR v28.4s, v26.4s, #16
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LD1 {v3.4h}, [x2], x9
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UZP2 v29.8h, v28.8h, v28.8h
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UZP1 v28.8h, v28.8h, v28.8h
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mov v26.16b, v20.16b
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LD1 {v4.4h}, [x0], x8
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LD1 {v5.4h}, [x2], x9
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LD1 {v6.4h}, [x0], x8
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LD1 {v7.4h}, [x2], x9
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LD1 {v8.4h}, [x0], x8
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LD1 {v9.4h}, [x2], x9
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MOV x0, x10
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MOV x2, x11
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LD1 {v10.4h}, [x1], #8
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MOV x10, x1
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LD1 {v11.4h}, [x12], #8
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ADD x1, x1, #504
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MOV x11, x12
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LD1 {v12.4h}, [x1], x8
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ADD x12, x12, #248
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LD1 {v13.4h}, [x12], x9
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LD1 {v14.4h}, [x1], x8
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LD1 {v15.4h}, [x12], x9
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LD1 {v16.4h}, [x1], x8
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LD1 {v17.4h}, [x12], x9
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LD1 {v18.4h}, [x1], x8
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SUB x6, x6, #2
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LD1 {v19.4h}, [x12], x9
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MOV x1, x10
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MOV x12, x11
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LOOP_1:
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sMLAL v26.4s, v0.4h, v1.4h
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ST1 {v28.h}[0], [x3], x5
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sMLAL v26.4s, v2.4h, v3.4h
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LD1 {v0.4h}, [x0], #8
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sMLAL v26.4s, v5.4h, v4.4h
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sMLAL v26.4s, v7.4h, v6.4h
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ST1 {v28.h}[1], [x3], x5
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MOV x10, x0
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LD1 {v1.4h}, [x2], #8
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ADD x0, x0, #504
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sMLAL v26.4s, v9.4h, v8.4h
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ST1 {v28.h}[2], [x3], x5
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sMLAL v26.4s, v10.4h, v11.4h
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ST1 {v28.h}[3], [x3], x5
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MOV x11, x2
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LD1 {v2.4h}, [x0], x8
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ADD x2, x2, #248
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sMLAL v26.4s, v12.4h, v13.4h
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LD1 {v3.4h}, [x2], x9
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sMLAL v26.4s, v15.4h, v14.4h
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sMLAL v26.4s, v17.4h, v16.4h
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LD1 {v4.4h}, [x0], x8
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sMLAL v26.4s, v19.4h, v18.4h
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LD1 {v5.4h}, [x2], x9
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LD1 {v6.4h}, [x0], x8
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sQshL v26.4s, v26.4s, v22.4s
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sshR v28.4s, v26.4s, #16
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LD1 {v7.4h}, [x2], x9
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mov v26.16b, v20.16b
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UZP2 v29.8h, v28.8h, v28.8h
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UZP1 v28.8h, v28.8h, v28.8h
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sMLAL v26.4s, v0.4h, v1.4h
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sMLAL v26.4s, v2.4h, v3.4h
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LD1 {v8.4h}, [x0], x8
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sMLAL v26.4s, v5.4h, v4.4h
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sMLAL v26.4s, v7.4h, v6.4h
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LD1 {v9.4h}, [x2], x9
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LD1 {v10.4h}, [x1], #8
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sMLAL v26.4s, v9.4h, v8.4h
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MOV x2, x11
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LD1 {v11.4h}, [x12], #8
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MOV x0, x10
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MOV x10, x1
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ADD x1, x1, #504
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MOV x11, x12
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LD1 {v12.4h}, [x1], x8
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ADD x12, x12, #248
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LD1 {v13.4h}, [x12], x9
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sMLAL v26.4s, v10.4h, v11.4h
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LD1 {v14.4h}, [x1], x8
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sMLAL v26.4s, v12.4h, v13.4h
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LD1 {v15.4h}, [x12], x9
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LD1 {v16.4h}, [x1], x8
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sMLAL v26.4s, v15.4h, v14.4h
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LD1 {v17.4h}, [x12], x9
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LD1 {v18.4h}, [x1], x8
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sMLAL v26.4s, v17.4h, v16.4h
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LD1 {v19.4h}, [x12], x9
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MOV x1, x10
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sMLAL v26.4s, v19.4h, v18.4h
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ST1 {v28.h}[0], [x3], x5
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MOV x12, x11
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LD1 {v0.4h}, [x0], #8
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LD1 {v1.4h}, [x2], #8
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sQshL v26.4s, v26.4s, v22.4s
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ST1 {v28.h}[1], [x3], x5
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MOV x10, x0
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ST1 {v28.h}[2], [x3], x5
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ADD x0, x0, #504
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ST1 {v28.h}[3], [x3], x5
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MOV x11, x2
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sshR v28.4s, v26.4s, #16
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LD1 {v2.4h}, [x0], x8
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ADD x2, x2, #248
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LD1 {v3.4h}, [x2], x9
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LD1 {v4.4h}, [x0], x8
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LD1 {v5.4h}, [x2], x9
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LD1 {v6.4h}, [x0], x8
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LD1 {v7.4h}, [x2], x9
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LD1 {v8.4h}, [x0], x8
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LD1 {v9.4h}, [x2], x9
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UZP2 v29.8h, v28.8h, v28.8h
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UZP1 v28.8h, v28.8h, v28.8h
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mov v26.16b, v20.16b
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MOV x0, x10
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LD1 {v10.4h}, [x1], #8
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MOV x2, x11
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MOV x10, x1
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LD1 {v11.4h}, [x12], #8
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ADD x1, x1, #504
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MOV x11, x12
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LD1 {v12.4h}, [x1], x8
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ADD x12, x12, #248
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LD1 {v13.4h}, [x12], x9
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LD1 {v14.4h}, [x1], x8
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LD1 {v15.4h}, [x12], x9
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LD1 {v16.4h}, [x1], x8
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LD1 {v17.4h}, [x12], x9
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SUBS x6, x6, #2
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LD1 {v18.4h}, [x1], x8
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MOV x1, x10
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LD1 {v19.4h}, [x12], x9
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MOV x12, x11
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BGT LOOP_1
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sMLAL v26.4s, v0.4h, v1.4h
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ST1 {v28.h}[0], [x3], x5
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sMLAL v26.4s, v2.4h, v3.4h
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|
|
sMLAL v26.4s, v5.4h, v4.4h
|
||
|
|
ST1 {v28.h}[1], [x3], x5
|
||
|
|
sMLAL v26.4s, v7.4h, v6.4h
|
||
|
|
|
||
|
|
sMLAL v26.4s, v9.4h, v8.4h
|
||
|
|
ST1 {v28.h}[2], [x3], x5
|
||
|
|
sMLAL v26.4s, v10.4h, v11.4h
|
||
|
|
|
||
|
|
sMLAL v26.4s, v12.4h, v13.4h
|
||
|
|
ST1 {v28.h}[3], [x3], x5
|
||
|
|
sMLAL v26.4s, v15.4h, v14.4h
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
sMLAL v26.4s, v17.4h, v16.4h
|
||
|
|
|
||
|
|
sMLAL v26.4s, v19.4h, v18.4h
|
||
|
|
|
||
|
|
sQshL v26.4s, v26.4s, v22.4s
|
||
|
|
|
||
|
|
sshR v28.4s, v26.4s, #16
|
||
|
|
|
||
|
|
UZP2 v29.8h, v28.8h, v28.8h
|
||
|
|
UZP1 v28.8h, v28.8h, v28.8h
|
||
|
|
|
||
|
|
|
||
|
|
ST1 {v28.h}[0], [x3], x5
|
||
|
|
ST1 {v28.h}[1], [x3], x5
|
||
|
|
ST1 {v28.h}[2], [x3], x5
|
||
|
|
ST1 {v28.h}[3], [x3], x5
|
||
|
|
|
||
|
|
|
||
|
|
pop_v_regs
|
||
|
|
ret
|
||
|
|
|