290 lines
7.9 KiB
ArmAsm
290 lines
7.9 KiB
ArmAsm
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/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <context.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL1.
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* -----------------------------------------------------------------------------
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*/
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.globl bl1_exceptions
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vector_base bl1_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSP0
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSP0
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSP0
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionSPx
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqSPx
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqSPx
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/* Expect only SMC exceptions */
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH64_SMC
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b.ne unexpected_sync_exception
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b smc_handler64
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end_vector_entry SynchronousExceptionA64
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA64
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA64
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SynchronousExceptionA32
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry IrqA32
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry FiqA32
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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no_ret plat_panic_handler
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end_vector_entry SErrorA32
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func smc_handler64
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/* ----------------------------------------------
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* Detect if this is a RUN_IMAGE or other SMC.
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* ----------------------------------------------
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*/
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mov x30, #BL1_SMC_RUN_IMAGE
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cmp x30, x0
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b.ne smc_handler
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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mrs x30, scr_el3
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tst x30, #SCR_NS_BIT
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b.ne unexpected_sync_exception
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/* ----------------------------------------------
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* Handling RUN_IMAGE SMC. First switch back to
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* SP_EL0 for the C runtime stack.
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* ----------------------------------------------
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*/
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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msr spsel, #MODE_SP_EL0
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mov sp, x30
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/* ---------------------------------------------------------------------
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* Pass EL3 control to next BL image.
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* Here it expects X1 with the address of a entry_point_info_t
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* structure describing the next BL image entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov x20, x1
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mov x0, x20
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bl bl1_print_next_bl_ep_info
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne unexpected_sync_exception
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bl disable_mmu_icache_el3
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tlbi alle3
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dsb ish /* ERET implies ISB, so it is not needed here */
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov x0, x20
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bl bl1_plat_prepare_exit
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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exception_return
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endfunc smc_handler64
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unexpected_sync_exception:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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no_ret plat_panic_handler
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/* -----------------------------------------------------
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* Save Secure/Normal world context and jump to
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* BL1 SMC handler.
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* -----------------------------------------------------
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*/
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smc_handler:
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/* -----------------------------------------------------
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* Save x0-x29 and ARMv8.3-PAuth (if enabled) registers.
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* If Secure Cycle Counter is not disabled in MDCR_EL3
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* when ARMv8.5-PMU is implemented, save PMCR_EL0 and
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* disable Cycle Counter.
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* TODO: Revisit to store only SMCCC specified registers.
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* -----------------------------------------------------
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*/
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bl save_gp_pmcr_pauth_regs
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#if ENABLE_PAUTH
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/* -----------------------------------------------------
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* Load and program stored APIAKey firmware key.
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* Re-enable pointer authentication in EL3, as it was
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* disabled before jumping to the next boot image.
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* -----------------------------------------------------
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*/
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bl pauth_load_bl1_apiakey_enable
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#endif
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/* -----------------------------------------------------
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* Populate the parameters for the SMC handler. We
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* already have x0-x4 in place. x5 will point to a
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* cookie (not used now). x6 will point to the context
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* structure (SP_EL3) and x7 will contain flags we need
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* to pass to the handler.
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* -----------------------------------------------------
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*/
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mov x5, xzr
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mov x6, sp
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/* -----------------------------------------------------
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* Restore the saved C runtime stack value which will
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* become the new SP_EL0 i.e. EL3 runtime stack. It was
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* saved in the 'cpu_context' structure prior to the last
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* ERET from EL3.
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* -----------------------------------------------------
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*/
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ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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/* ---------------------------------------------
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* Switch back to SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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*/
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msr spsel, #MODE_SP_EL0
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mov sp, x12
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/* -----------------------------------------------------
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* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
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* is a world switch during SMC handling.
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* -----------------------------------------------------
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*/
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mrs x16, spsr_el3
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mrs x17, elr_el3
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mrs x18, scr_el3
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stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
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/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
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bfi x7, x18, #0, #1
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/* -----------------------------------------------------
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* Go to BL1 SMC handler.
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* -----------------------------------------------------
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*/
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bl bl1_smc_handler
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/* -----------------------------------------------------
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* Do the transition to next BL image.
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* -----------------------------------------------------
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*/
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b el3_exit
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