274 lines
10 KiB
ArmAsm
274 lines
10 KiB
ArmAsm
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@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@*******************************************************************************
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@* @file
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@* ihevc_inter_pred_chroma_copy_neon.s
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@*
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@* @brief
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@* contains function definitions for inter prediction interpolation.
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@* functions are coded using neon intrinsics and can be compiled using
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@* rvct
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@*
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@* @author
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@* yogeswaran rs
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@*
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@* @par list of functions:
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@*
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@*
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@* @remarks
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@* none
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@*
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@*******************************************************************************
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@*/
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@/**
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@*******************************************************************************
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@*
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@* @brief
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@* chroma interprediction filter for copy
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@*
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@* @par description:
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@* copies the array of width 'wd' and height 'ht' from the location pointed
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@* by 'src' to the location pointed by 'dst'
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@*
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@* @param[in] pu1_src
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@* uword8 pointer to the source
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@*
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@* @param[out] pu1_dst
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@* uword8 pointer to the destination
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@*
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@* @param[in] src_strd
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@* integer source stride
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@*
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@* @param[in] dst_strd
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@* integer destination stride
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@*
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@* @param[in] pi1_coeff
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@* word8 pointer to the filter coefficients
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@*
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@* @param[in] ht
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@* integer height of the array
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@*
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@* @param[in] wd
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@* integer width of the array
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@*
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@* @returns
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@*
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@* @remarks
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@* none
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@*
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@*******************************************************************************
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@*/
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@void ihevc_inter_pred_chroma_copy( uword8 *pu1_src,
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@ uword8 *pu1_dst,
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@ word32 src_strd,
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@ word32 dst_strd,
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@ word8 *pi1_coeff,
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@ word32 ht,
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@ word32 wd)
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@**************variables vs registers*****************************************
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@ r0 => *pu1_src
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@ r1 => *pu1_dst
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@ r2 => src_strd
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@ r3 => dst_strd
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@ r4 => *pi1_coeff
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@ r5 => ht
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@ r6 => wd
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.equ ht_offset, 44
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.equ wd_offset, 48
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.text
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.align 4
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.globl ihevc_inter_pred_chroma_copy_a9q
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.type ihevc_inter_pred_chroma_copy_a9q, %function
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ihevc_inter_pred_chroma_copy_a9q:
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stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
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ldr r12,[sp,#wd_offset] @loads wd
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lsl r12,r12,#1
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ldr r7,[sp,#ht_offset] @loads ht
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cmp r7,#0 @checks ht == 0
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ble end_loops
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and r8,r7,#3 @check ht for mul of 2
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sub r7,r7,r8 @check the rounded height value
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tst r12,#15 @checks wd for multiples for 4 & 8
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beq core_loop_wd_16
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tst r12,#7 @checks wd for multiples for 4 & 8
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beq core_loop_wd_8
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sub r11,r12,#4
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cmp r7,#0
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beq outer_loop_wd_4_ht_2
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outer_loop_wd_4:
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subs r4,r12,#0 @checks wd == 0
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ble end_inner_loop_wd_4
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inner_loop_wd_4:
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vld1.32 {d0[0]},[r0] @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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add r5,r0,r2 @pu1_src_tmp += src_strd
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.32 {d0[0]},[r1] @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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vld1.32 {d0[0]},[r5],r2 @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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add r0,r0,#4 @pu1_src += 4
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vst1.32 {d0[0]},[r6],r3 @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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vld1.32 {d0[0]},[r5],r2 @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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subs r4,r4,#4 @(wd -4)
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vst1.32 {d0[0]},[r6],r3 @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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vld1.32 {d0[0]},[r5],r2 @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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add r1,r1,#4 @pu1_dst += 4
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vst1.32 {d0[0]},[r6],r3 @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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bgt inner_loop_wd_4
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end_inner_loop_wd_4:
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subs r7,r7,#4 @ht - 4
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sub r0,r5,r11 @pu1_src = pu1_src_tmp
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sub r1,r6,r11 @pu1_dst = pu1_dst_tmp
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bgt outer_loop_wd_4
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cmp r8,#0
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bgt outer_loop_wd_4_ht_2
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end_loops:
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ldmfd sp!,{r4-r12,r15} @reload the registers from sp
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outer_loop_wd_4_ht_2:
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subs r4,r12,#0 @checks wd == 0
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ble end_loops
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inner_loop_wd_4_ht_2:
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vld1.32 {d0[0]},[r0] @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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add r5,r0,r2 @pu1_src_tmp += src_strd
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.32 {d0[0]},[r1] @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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vld1.32 {d0[0]},[r5],r2 @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp, 0)
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add r0,r0,#4 @pu1_src += 4
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vst1.32 {d0[0]},[r6],r3 @vst1_lane_u32((uint32_t *)pu1_dst_tmp, src_tmp, 0)
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subs r4,r4,#4 @(wd -4)
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add r1,r1,#4 @pu1_dst += 4
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bgt inner_loop_wd_4_ht_2
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b end_loops
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core_loop_wd_8:
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sub r11,r12,#8
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cmp r7,#0
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beq outer_loop_wd_8_ht_2
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outer_loop_wd_8:
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subs r4,r12,#0 @checks wd
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ble end_inner_loop_wd_8
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inner_loop_wd_8:
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add r5,r0,r2 @pu1_src_tmp += src_strd
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vld1.8 {d0},[r0]! @vld1_u8(pu1_src_tmp)
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.8 {d0},[r1]! @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {d1},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {d1},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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subs r4,r4,#8 @wd - 8(loop condition)
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vld1.8 {d2},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {d2},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {d3},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {d3},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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bgt inner_loop_wd_8
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end_inner_loop_wd_8:
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subs r7,r7,#4 @ht -= 4
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sub r0,r5,r11 @pu1_src = pu1_src_tmp
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sub r1,r6,r11 @pu1_dst = pu1_dst_tmp
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bgt outer_loop_wd_8
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cmp r8,#0
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bgt outer_loop_wd_8_ht_2
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b end_loops
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outer_loop_wd_8_ht_2:
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subs r4,r12,#0 @checks wd
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ble end_loops
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inner_loop_wd_8_ht_2:
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add r5,r0,r2 @pu1_src_tmp += src_strd
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vld1.8 {d0},[r0]! @vld1_u8(pu1_src_tmp)
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.8 {d0},[r1]! @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {d1},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {d1},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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@subs r4,r4,#8 @wd - 8(loop condition)
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@bgt inner_loop_wd_8_ht_2
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b end_loops
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core_loop_wd_16:
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sub r11,r12,#16
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cmp r7,#0
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beq outer_loop_wd_16_ht_2
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outer_loop_wd_16:
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subs r4,r12,#0 @checks wd
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ble end_inner_loop_wd_16
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inner_loop_wd_16:
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add r5,r0,r2 @pu1_src_tmp += src_strd
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vld1.8 {q0},[r0]! @vld1_u8(pu1_src_tmp)
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.8 {q0},[r1]! @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {q1},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {q1},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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subs r4,r4,#16 @wd - 16(loop condition)
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vld1.8 {q2},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {q2},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {q3},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {q3},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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bgt inner_loop_wd_16
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end_inner_loop_wd_16:
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subs r7,r7,#4 @ht -= 4
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sub r0,r5,r11 @pu1_src = pu1_src_tmp
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sub r1,r6,r11 @pu1_dst = pu1_dst_tmp
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bgt outer_loop_wd_16
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cmp r8,#0
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bgt outer_loop_wd_16_ht_2
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b end_loops
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outer_loop_wd_16_ht_2:
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subs r4,r12,#0 @checks wd
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ble end_loops
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inner_loop_wd_16_ht_2:
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add r5,r0,r2 @pu1_src_tmp += src_strd
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vld1.8 {q0},[r0]! @vld1_u8(pu1_src_tmp)
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add r6,r1,r3 @pu1_dst_tmp += dst_strd
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vst1.8 {q0},[r1]! @vst1_u8(pu1_dst_tmp, tmp_src)
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vld1.8 {q1},[r5],r2 @vld1_u8(pu1_src_tmp)
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vst1.8 {q1},[r6],r3 @vst1_u8(pu1_dst_tmp, tmp_src)
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@subs r4,r4,#16 @wd - 16(loop condition)
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@bgt inner_loop_wd_16_ht_2
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ldmfd sp!,{r4-r12,r15} @reload the registers from sp
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