260 lines
12 KiB
ArmAsm
260 lines
12 KiB
ArmAsm
;==================================================================
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; Copyright ARM Ltd 2005. All rights reserved.
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;
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; Cortex-A8 Dhrystone example - Startup Code
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;==================================================================
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PRESERVE8
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AREA CORTEXA8, CODE, READONLY
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ENTRY
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; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UNDEF EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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;==================================================================
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; Disable Cortex-A8 MMU if enabled
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;==================================================================
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EXPORT Start
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Start
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MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Register into r0
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TST r0, #0x1 ; Is the MMU enabled?
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BICNE r0, r0, #0x1 ; Clear bit 0
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MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
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;==================================================================
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; Initialise Supervisor Mode Stack
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; Note stack must be 8 byte aligned.
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;==================================================================
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IMPORT ||Image$$STACK$$ZI$$Limit|| ; Linker symbol from scatter file
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LDR SP, =||Image$$STACK$$ZI$$Limit||
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;==================================================================
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; TLB maintenance, Invalidate Data and Instruction TLB's
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;==================================================================
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MOV r0,#0
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MCR p15, 0, r0, c8, c7, 0 ; Cortex-A8 I-TLB and D-TLB invalidation
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;==================================================================
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; Cache Invalidation code for Cortex-A8
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;==================================================================
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; Invalidate L1 Instruction Cache
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MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR
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TST r0, #0x3 ; Harvard Cache?
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MOV r0, #0
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MCRNE p15, 0, r0, c7, c5, 0 ; Invalidate Instruction Cache
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; Invalidate Data/Unified Caches
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MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR
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ANDS r3, r0, #&7000000
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MOV r3, r3, LSR #23 ; Total cache levels << 1
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BEQ Finished
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MOV r10, #0 ; R10 holds current cache level << 1
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Loop1 ADD r2, r10, r10, LSR #1 ; R2 holds cache "Set" position
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MOV r1, r0, LSR r2 ; Bottom 3 bits are the Cache-type for this level
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AND r1, R1, #7 ; Get those 3 bits alone
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CMP r1, #2
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BLT Skip ; No cache or only instruction cache at this level
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MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register
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MOV r1, #0
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MCR p15, 0, r1, c7, c5, 4 ; PrefetchFlush to sync the change to the CacheSizeID reg
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MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register
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AND r2, r1, #&7 ; Extract the line length field
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ADD r2, r2, #4 ; Add 4 for the line length offset (log2 16 bytes)
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LDR r4, =0x3FF
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ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned)
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CLZ r5, r4 ; R5 is the bit position of the way size increment
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LDR r7, =0x00007FFF
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ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop2 MOV r9, r4 ; R9 working copy of the max way size (right aligned)
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Loop3 ORR r11, r10, r9, LSL r5 ; Factor in the Way number and cache number into R11
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ORR r11, r11, r7, LSL r2 ; Factor in the Set number
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MCR p15, 0, r11, c7, c14, 2 ; Clean and Invalidate by set/way
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SUBS r9, r9, #1 ; Decrement the Way number
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BGE Loop3
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SUBS r7, r7, #1 ; Decrement the Set number
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BGE Loop2
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Skip ADD r10, r10, #2 ; increment the cache number
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CMP r3, r10
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BGT Loop1
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Finished
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;===================================================================
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; Cortex-A8 MMU Configuration
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; Set translation table base
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;===================================================================
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IMPORT ||Image$$TTB$$ZI$$Base|| ; from scatter file.;
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; Cortex-A8 supports two translation tables
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; Configure translation table base (TTB) control register cp15,c2
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; to a value of all zeros, indicates we are using TTB register 0.
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MOV r0,#0x0
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MCR p15, 0, r0, c2, c0, 2
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; write the address of our page table base to TTB register 0.;
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; We are setting to outer-noncachable [4:3] is zero
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LDR r0,=||Image$$TTB$$ZI$$Base||
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MCR p15, 0, r0, c2, c0, 0
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;===================================================================
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; Cortex-A8 PAGE TABLE generation, using standard Arch v6 tables
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;
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; AP[11:10] - Access Permissions = b11, Read/Write Access
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; Domain[8:5] - Domain = b1111, Domain 15
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; Type[1:0] - Descriptor Type = b10, 1Mb descriptors
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;
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; TEX C B
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; 000 0 0 Strongly Ordered
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; 001 1 1 Outer and inner write back, write allocate Normal
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;===================================================================
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LDR r1,=0xfff ; loop counter
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LDR r2,=2_00000000000000000000110111100010
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; r0 contains the address of the translation table base
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; r1 is loop counter
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; r2 is level1 descriptor (bits 19:0)
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; use loop counter to create 4096 individual table entries
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; this writes from address 0x7FFC down to 0x4000 in word steps (4bytes).
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init_ttb_1
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ORR r3, r2, r1, LSL#20 ; r3 now contains full level1 descriptor to write
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STR r3, [r0, r1, LSL#2] ; str table entry at TTB base + loopcount*4
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SUBS r1, r1, #1 ; decrement loop counter
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BPL init_ttb_1
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; In this example we will change the cacheable attribute in the first descriptor.
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; Virtual memory from 0 to 1MB will be cacheable (write back mode).
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; TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate.
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ORR r3,r3,#2_0000000001100 ; Set CB bits
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ORR r3,r3,#2_1000000000000 ; Set TEX bits
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STR r3,[r0]
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ADD r2, r3, #0x100000 ; alter r3 to have correct base address for second descriptor (flat mapping)
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STR r2, [r0, #4] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x200000 ; alter r3 to have correct base address for 3 descriptor (flat mapping)
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STR r2, [r0, #8] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x300000 ; alter r3 to have correct base address for 4 descriptor (flat mapping)
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STR r2, [r0, #0xc] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x400000 ; alter r3 to have correct base address for 5 descriptor (flat mapping)
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STR r2, [r0, #0x10] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x500000 ; alter r3 to have correct base address for 6 descriptor (flat mapping)
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STR r2, [r0, #0x14] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x600000 ; alter r3 to have correct base address for 7 descriptor (flat mapping)
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STR r2, [r0, #0x18] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x700000 ; alter r3 to have correct base address for 8 descriptor (flat mapping)
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STR r2, [r0, #0x1c] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x800000 ; alter r3 to have correct base address for 9 descriptor (flat mapping)
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STR r2, [r0, #0x20] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0x900000 ; alter r3 to have correct base address for 10 descriptor (flat mapping)
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STR r2, [r0, #0x24] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0xa00000 ; alter r3 to have correct base address for 11 descriptor (flat mapping)
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STR r2, [r0, #0x28] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0xb00000 ; alter r3 to have correct base address for 12 descriptor (flat mapping)
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STR r2, [r0, #0x2c] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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ADD r2, r3, #0xc00000 ; alter r3 to have correct base address for 13 descriptor (flat mapping)
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STR r2, [r0, #0x30] ; store the new descriptor at r0 + 4 (overwrite second section descriptor)
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;===================================================================
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; Setup domain control register - Enable all domains to client mode
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;===================================================================
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MRC p15, 0, r0, c3, c0, 0 ; Read Domain Access Control Register
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LDR r0, =0x55555555 ; Initialize every domain entry to b01 (client)
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MCR p15, 0, r0, c3, c0, 0 ; Write Domain Access Control Register
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;===================================================================
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; Setup L2 Cache - L2 Cache Auxiliary Control
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;===================================================================
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MOV r0, #0
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;MCR p15, 1, r0, c9, c0, 2 ; Write L2 Auxilary Control Register
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;==================================================================
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; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
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; Enables Full Access i.e. in both priv and non priv modes
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;==================================================================
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MRC p15, 0, r0, c1, c0, 2 ; read CP access register
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ORR r0, r0, #(0x3 <<20) ; enable access CP 10
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ORR r0, r0, #(0x3 <<22) ; enable access CP 11
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MCR p15, 0, r0, c1, c0, 2 ; write CP access register back
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;==================================================================
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; Switch on the VFP and Neon Hardware
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;=================================================================
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MOV r0, #0 ; Set up a register
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ORR r0, r0, #(0x1 << 30)
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FMXR FPEXC, r0 ; Write FPEXC register, EN bit set.
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;===================================================================
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; Enable MMU and Branch to __main
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;===================================================================
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IMPORT __main ; before MMU enabled import label to __main
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LDR r12,=__main ; save this in register for possible long jump
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MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0
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ORR r0, r0, #0x1 ; enable MMU before scatter loading
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MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
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; Now the MMU is enabled, virtual to physical address translations will occur.
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; This will affect the next instruction fetches.
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;
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; The two instructions currently in the ARM pipeline will have been fetched
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; before the MMU was enabled. This property is useful because the next two
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; instructions are safe even if new instruction fetches fail. If this routine
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; was mapped out of the new virtual memory map, the branch to __main would
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; still succeed.
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BX r12 ; branch to __main C library entry point
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END ; mark the end of this file
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