244 lines
9.5 KiB
C
244 lines
9.5 KiB
C
/*
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Copyright (c) 2009, 2010, 2011, 2013 STMicroelectronics
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Written by Christophe Lyon
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#if defined(__arm__) || defined(__aarch64__)
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#include <arm_neon.h>
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#else
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#include "stm-arm-neon.h"
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#endif
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#include "stm-arm-neon-ref.h"
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void exec_vldX_lane (void)
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{
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/* In this case, input variables are arrays of vectors */
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#define DECL_VLDX_LANE(T1, W, N, X) \
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VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
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VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector_src, T1, W, N, X); \
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VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
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/* We need to use a temporary result buffer (result_bis), because
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the one used for other tests is not large enough. A subset of the
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result data is moved from result_bis to result, and it is this
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subset which is used to check the actual behaviour. The next
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macro enables to move another chunk of data from result_bis to
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result. */
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#define TEST_VLDX_LANE(Q, T1, T2, W, N, X, L) \
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memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, \
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sizeof(VECT_VAR(buffer_src, T1, W, N))); \
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\
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VECT_ARRAY_VAR(vector_src, T1, W, N, X) = \
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vld##X##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N)); \
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\
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VECT_ARRAY_VAR(vector, T1, W, N, X) = \
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/* Use dedicated init buffer, of size X */ \
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vld##X##Q##_lane_##T2##W(VECT_VAR(buffer_vld##X##_lane, T1, W, X), \
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VECT_ARRAY_VAR(vector_src, T1, W, N, X), \
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L); \
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vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
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VECT_ARRAY_VAR(vector, T1, W, N, X)); \
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memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
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sizeof(VECT_VAR(result, T1, W, N)))
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/* Overwrite "result" with the contents of "result_bis"[Y] */
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#define TEST_EXTRA_CHUNK(T1, W, N, X, Y) \
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memcpy(VECT_VAR(result, T1, W, N), \
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&(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
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sizeof(VECT_VAR(result, T1, W, N)));
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/* With ARM RVCT, we need to declare variables before any executable
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statement */
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/* We need all variants in 64 bits, but there is no 64x2 variant */
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#define DECL_ALL_VLDX_LANE(X) \
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DECL_VLDX_LANE(int, 8, 8, X); \
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DECL_VLDX_LANE(int, 16, 4, X); \
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DECL_VLDX_LANE(int, 32, 2, X); \
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DECL_VLDX_LANE(uint, 8, 8, X); \
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DECL_VLDX_LANE(uint, 16, 4, X); \
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DECL_VLDX_LANE(uint, 32, 2, X); \
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DECL_VLDX_LANE(poly, 8, 8, X); \
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DECL_VLDX_LANE(poly, 16, 4, X); \
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DECL_VLDX_LANE(int, 16, 8, X); \
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DECL_VLDX_LANE(int, 32, 4, X); \
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DECL_VLDX_LANE(uint, 16, 8, X); \
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DECL_VLDX_LANE(uint, 32, 4, X); \
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DECL_VLDX_LANE(poly, 16, 8, X); \
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DECL_VLDX_LANE(float, 32, 2, X); \
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DECL_VLDX_LANE(float, 32, 4, X)
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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#define DECL_ALL_VLDX_LANE_FP16(X) \
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DECL_VLDX_LANE(float, 16, 4, X); \
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DECL_VLDX_LANE(float, 16, 8, X)
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#endif
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/* Add some padding to try to catch out of bound accesses. */
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/* Use an array instead of a plain char to comply with rvct
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constraints. */
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#define ARRAY1(V, T, W, N) VECT_VAR_DECL(V,T,W,N)[1]={42}
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#define DUMMY_ARRAY(V, T, W, N, L) \
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VECT_VAR_DECL(V,T,W,N)[N*L]={0}; \
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ARRAY1(V##_pad,T,W,N)
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/* Use the same lanes regardless of the size of the array (X), for
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simplicity */
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#define TEST_ALL_VLDX_LANE(X) \
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TEST_VLDX_LANE(, int, s, 8, 8, X, 7); \
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TEST_VLDX_LANE(, int, s, 16, 4, X, 2); \
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TEST_VLDX_LANE(, int, s, 32, 2, X, 0); \
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TEST_VLDX_LANE(, uint, u, 8, 8, X, 4); \
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TEST_VLDX_LANE(, uint, u, 16, 4, X, 3); \
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TEST_VLDX_LANE(, uint, u, 32, 2, X, 1); \
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TEST_VLDX_LANE(, poly, p, 8, 8, X, 4); \
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TEST_VLDX_LANE(, poly, p, 16, 4, X, 3); \
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TEST_VLDX_LANE(q, int, s, 16, 8, X, 6); \
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TEST_VLDX_LANE(q, int, s, 32, 4, X, 2); \
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TEST_VLDX_LANE(q, uint, u, 16, 8, X, 5); \
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TEST_VLDX_LANE(q, uint, u, 32, 4, X, 0); \
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TEST_VLDX_LANE(q, poly, p, 16, 8, X, 5); \
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TEST_VLDX_LANE(, float, f, 32, 2, X, 0); \
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TEST_VLDX_LANE(q, float, f, 32, 4, X, 2)
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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#define TEST_ALL_VLDX_LANE_FP16(X) \
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TEST_VLDX_LANE(, float, f, 16, 4, X, 0); \
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TEST_VLDX_LANE(q, float, f, 16, 8, X, 2)
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#endif
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#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
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TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
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TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
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TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
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TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
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TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
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TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
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TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
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TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
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TEST_EXTRA_CHUNK(int, 16, 8, X, Y); \
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TEST_EXTRA_CHUNK(int, 32, 4, X, Y); \
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TEST_EXTRA_CHUNK(uint, 16, 8, X, Y); \
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TEST_EXTRA_CHUNK(uint, 32, 4, X, Y); \
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TEST_EXTRA_CHUNK(poly, 16, 8, X, Y); \
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TEST_EXTRA_CHUNK(float, 32, 2, X, Y); \
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TEST_EXTRA_CHUNK(float, 32, 4, X, Y)
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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#define TEST_ALL_EXTRA_CHUNKS_FP16(X, Y) \
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TEST_EXTRA_CHUNK(float, 16, 4, X, Y); \
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TEST_EXTRA_CHUNK(float, 16, 8, X, Y)
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#endif
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/* Declare the temporary buffers / variables */
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DECL_ALL_VLDX_LANE(2);
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DECL_ALL_VLDX_LANE(3);
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DECL_ALL_VLDX_LANE(4);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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DECL_ALL_VLDX_LANE_FP16(2);
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DECL_ALL_VLDX_LANE_FP16(3);
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DECL_ALL_VLDX_LANE_FP16(4);
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#endif
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/* Define dummy input arrays, large enough for x4 vectors */
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DUMMY_ARRAY(buffer_src, int, 8, 8, 4);
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DUMMY_ARRAY(buffer_src, int, 16, 4, 4);
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DUMMY_ARRAY(buffer_src, int, 32, 2, 4);
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DUMMY_ARRAY(buffer_src, uint, 8, 8, 4);
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DUMMY_ARRAY(buffer_src, uint, 16, 4, 4);
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DUMMY_ARRAY(buffer_src, uint, 32, 2, 4);
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DUMMY_ARRAY(buffer_src, poly, 8, 8, 4);
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DUMMY_ARRAY(buffer_src, poly, 16, 4, 4);
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DUMMY_ARRAY(buffer_src, int, 16, 8, 4);
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DUMMY_ARRAY(buffer_src, int, 32, 4, 4);
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DUMMY_ARRAY(buffer_src, uint, 16, 8, 4);
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DUMMY_ARRAY(buffer_src, uint, 32, 4, 4);
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DUMMY_ARRAY(buffer_src, poly, 16, 8, 4);
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DUMMY_ARRAY(buffer_src, float, 32, 2, 4);
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DUMMY_ARRAY(buffer_src, float, 32, 4, 4);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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DUMMY_ARRAY(buffer_src, float, 16, 4, 4);
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DUMMY_ARRAY(buffer_src, float, 16, 8, 4);
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#endif
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/* Check vld2_lane/vld2q_lane */
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clean_results ();
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#define TEST_MSG "VLD2_LANE/VLD2Q_LANE"
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TEST_ALL_VLDX_LANE(2);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_VLDX_LANE_FP16(2);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 0");
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TEST_ALL_EXTRA_CHUNKS(2, 1);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(2, 1);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 1");
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/* Check vld3_lane/vld3q_lane */
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clean_results ();
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#undef TEST_MSG
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#define TEST_MSG "VLD3_LANE/VLD3Q_LANE"
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TEST_ALL_VLDX_LANE(3);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_VLDX_LANE_FP16(3);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 0");
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TEST_ALL_EXTRA_CHUNKS(3, 1);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(3, 1);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 1");
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TEST_ALL_EXTRA_CHUNKS(3, 2);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(3, 2);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 2");
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/* Check vld4_lane/vld4q_lane */
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clean_results ();
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#undef TEST_MSG
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#define TEST_MSG "VLD4_LANE/VLD4Q_LANE"
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TEST_ALL_VLDX_LANE(4);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_VLDX_LANE_FP16(4);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 0");
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TEST_ALL_EXTRA_CHUNKS(4, 1);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(4, 1);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 1");
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TEST_ALL_EXTRA_CHUNKS(4, 2);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(4, 2);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 2");
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TEST_ALL_EXTRA_CHUNKS(4, 3);
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#if defined(__ARM_FP16_FORMAT_IEEE) && ( ((__ARM_FP & 0x2) != 0) || ((__ARM_NEON_FP16_INTRINSICS & 1) != 0) )
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TEST_ALL_EXTRA_CHUNKS_FP16(4, 3);
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#endif
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dump_results_hex2 (TEST_MSG, " chunk 3");
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}
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