442 lines
13 KiB
C
442 lines
13 KiB
C
/*
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* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Contains generic routines to fix up the device tree blob passed on to
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* payloads like BL32 and BL33 (and further down the boot chain).
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* This allows to easily add PSCI nodes, when the original DT does not have
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* it or advertises another method.
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* Also it supports to add reserved memory nodes to describe memory that
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* is used by the secure world, so that non-secure software avoids using
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* that.
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <string.h>
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#include <libfdt.h>
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#include <arch.h>
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/console.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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static int append_psci_compatible(void *fdt, int offs, const char *str)
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{
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return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1);
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}
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/*
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* Those defines are for PSCI v0.1 legacy clients, which we expect to use
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* the same execution state (AArch32/AArch64) as TF-A.
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* Kernels running in AArch32 on an AArch64 TF-A should use PSCI v0.2.
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*/
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#ifdef __aarch64__
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#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH64
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#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH64
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#else
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#define PSCI_CPU_SUSPEND_FNID PSCI_CPU_SUSPEND_AARCH32
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#define PSCI_CPU_ON_FNID PSCI_CPU_ON_AARCH32
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#endif
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/*******************************************************************************
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* dt_add_psci_node() - Add a PSCI node into an existing device tree
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* @fdt: pointer to the device tree blob in memory
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*
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* Add a device tree node describing PSCI into the root level of an existing
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* device tree blob in memory.
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* This will add v0.1, v0.2 and v1.0 compatible strings and the standard
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* function IDs for v0.1 compatibility.
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* An existing PSCI node will not be touched, the function will return success
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* in this case. This function will not touch the /cpus enable methods, use
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* dt_add_psci_cpu_enable_methods() for that.
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*
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* Return: 0 on success, -1 otherwise.
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******************************************************************************/
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int dt_add_psci_node(void *fdt)
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{
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int offs;
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if (fdt_path_offset(fdt, "/psci") >= 0) {
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WARN("PSCI Device Tree node already exists!\n");
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return 0;
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}
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offs = fdt_path_offset(fdt, "/");
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if (offs < 0)
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return -1;
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offs = fdt_add_subnode(fdt, offs, "psci");
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if (offs < 0)
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return -1;
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if (append_psci_compatible(fdt, offs, "arm,psci-1.0"))
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return -1;
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if (append_psci_compatible(fdt, offs, "arm,psci-0.2"))
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return -1;
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if (append_psci_compatible(fdt, offs, "arm,psci"))
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return -1;
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if (fdt_setprop_string(fdt, offs, "method", "smc"))
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return -1;
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if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_FNID))
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return -1;
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if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF))
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return -1;
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if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_FNID))
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return -1;
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return 0;
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}
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/*
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* Find the first subnode that has a "device_type" property with the value
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* "cpu" and which's enable-method is not "psci" (yet).
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* Returns 0 if no such subnode is found, so all have already been patched
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* or none have to be patched in the first place.
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* Returns 1 if *one* such subnode has been found and successfully changed
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* to "psci".
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* Returns negative values on error.
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*
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* Call in a loop until it returns 0. Recalculate the node offset after
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* it has returned 1.
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*/
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static int dt_update_one_cpu_node(void *fdt, int offset)
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{
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int offs;
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/* Iterate over all subnodes to find those with device_type = "cpu". */
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for (offs = fdt_first_subnode(fdt, offset); offs >= 0;
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offs = fdt_next_subnode(fdt, offs)) {
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const char *prop;
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int len;
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int ret;
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prop = fdt_getprop(fdt, offs, "device_type", &len);
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if (prop == NULL)
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continue;
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if ((strcmp(prop, "cpu") != 0) || (len != 4))
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continue;
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/* Ignore any nodes which already use "psci". */
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prop = fdt_getprop(fdt, offs, "enable-method", &len);
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if ((prop != NULL) &&
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(strcmp(prop, "psci") == 0) && (len == 5))
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continue;
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ret = fdt_setprop_string(fdt, offs, "enable-method", "psci");
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if (ret < 0)
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return ret;
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/*
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* Subnode found and patched.
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* Restart to accommodate potentially changed offsets.
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*/
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return 1;
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}
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if (offs == -FDT_ERR_NOTFOUND)
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return 0;
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return offs;
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}
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/*******************************************************************************
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* dt_add_psci_cpu_enable_methods() - switch CPU nodes in DT to use PSCI
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* @fdt: pointer to the device tree blob in memory
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*
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* Iterate over all CPU device tree nodes (/cpus/cpu@x) in memory to change
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* the enable-method to PSCI. This will add the enable-method properties, if
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* required, or will change existing properties to read "psci".
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*
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* Return: 0 on success, or a negative error value otherwise.
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******************************************************************************/
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int dt_add_psci_cpu_enable_methods(void *fdt)
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{
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int offs, ret;
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do {
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offs = fdt_path_offset(fdt, "/cpus");
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if (offs < 0)
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return offs;
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ret = dt_update_one_cpu_node(fdt, offs);
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} while (ret > 0);
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return ret;
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}
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#define HIGH_BITS(x) ((sizeof(x) > 4) ? ((x) >> 32) : (typeof(x))0)
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/*******************************************************************************
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* fdt_add_reserved_memory() - reserve (secure) memory regions in DT
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* @dtb: pointer to the device tree blob in memory
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* @node_name: name of the subnode to be used
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* @base: physical base address of the reserved region
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* @size: size of the reserved region
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*
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* Add a region of memory to the /reserved-memory node in a device tree in
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* memory, creating that node if required. Each region goes into a subnode
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* of that node and has a @node_name, a @base address and a @size.
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* This will prevent any device tree consumer from using that memory. It
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* can be used to announce secure memory regions, as it adds the "no-map"
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* property to prevent mapping and speculative operations on that region.
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*
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* See reserved-memory/reserved-memory.txt in the (Linux kernel) DT binding
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* documentation for details.
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*
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* Return: 0 on success, a negative error value otherwise.
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******************************************************************************/
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int fdt_add_reserved_memory(void *dtb, const char *node_name,
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uintptr_t base, size_t size)
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{
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int offs = fdt_path_offset(dtb, "/reserved-memory");
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uint32_t addresses[3];
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if (offs < 0) { /* create if not existing yet */
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offs = fdt_add_subnode(dtb, 0, "reserved-memory");
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if (offs < 0)
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return offs;
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fdt_setprop_u32(dtb, offs, "#address-cells", 2);
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fdt_setprop_u32(dtb, offs, "#size-cells", 1);
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fdt_setprop(dtb, offs, "ranges", NULL, 0);
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}
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addresses[0] = cpu_to_fdt32(HIGH_BITS(base));
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addresses[1] = cpu_to_fdt32(base & 0xffffffff);
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addresses[2] = cpu_to_fdt32(size & 0xffffffff);
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offs = fdt_add_subnode(dtb, offs, node_name);
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fdt_setprop(dtb, offs, "no-map", NULL, 0);
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fdt_setprop(dtb, offs, "reg", addresses, 12);
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return 0;
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}
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/*******************************************************************************
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* fdt_add_cpu() Add a new CPU node to the DT
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* @dtb: Pointer to the device tree blob in memory
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* @parent: Offset of the parent node
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* @mpidr: MPIDR for the current CPU
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*
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* Create and add a new cpu node to a DTB.
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*
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* Return the offset of the new node or a negative value in case of error
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******************************************************************************/
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static int fdt_add_cpu(void *dtb, int parent, u_register_t mpidr)
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{
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int cpu_offs;
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int err;
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char snode_name[15];
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uint64_t reg_prop;
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reg_prop = mpidr & MPID_MASK & ~MPIDR_MT_MASK;
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snprintf(snode_name, sizeof(snode_name), "cpu@%x",
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(unsigned int)reg_prop);
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cpu_offs = fdt_add_subnode(dtb, parent, snode_name);
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if (cpu_offs < 0) {
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ERROR ("FDT: add subnode \"%s\" failed: %i\n",
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snode_name, cpu_offs);
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return cpu_offs;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "compatible", "arm,armv8");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"compatible", cpu_offs);
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return err;
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}
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err = fdt_setprop_u64(dtb, cpu_offs, "reg", reg_prop);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"reg", cpu_offs);
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return err;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "device_type", "cpu");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"device_type", cpu_offs);
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return err;
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}
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err = fdt_setprop_string(dtb, cpu_offs, "enable-method", "psci");
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"enable-method", cpu_offs);
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return err;
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}
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return cpu_offs;
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}
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/******************************************************************************
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* fdt_add_cpus_node() - Add the cpus node to the DTB
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* @dtb: pointer to the device tree blob in memory
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* @afflv0: Maximum number of threads per core (affinity level 0).
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* @afflv1: Maximum number of CPUs per cluster (affinity level 1).
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* @afflv2: Maximum number of clusters (affinity level 2).
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*
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* Iterate over all the possible MPIDs given the maximum affinity levels and
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* add a cpus node to the DTB with all the valid CPUs on the system.
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* If there is already a /cpus node, exit gracefully
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*
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* A system with two CPUs would generate a node equivalent or similar to:
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*
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* cpus {
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* #address-cells = <2>;
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* #size-cells = <0>;
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*
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* cpu0: cpu@0 {
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* compatible = "arm,armv8";
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* reg = <0x0 0x0>;
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* device_type = "cpu";
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* enable-method = "psci";
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* };
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* cpu1: cpu@10000 {
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* compatible = "arm,armv8";
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* reg = <0x0 0x100>;
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* device_type = "cpu";
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* enable-method = "psci";
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* };
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* };
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*
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* Full documentation about the CPU bindings can be found at:
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* https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt
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*
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* Return the offset of the node or a negative value on error.
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******************************************************************************/
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int fdt_add_cpus_node(void *dtb, unsigned int afflv0,
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unsigned int afflv1, unsigned int afflv2)
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{
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int offs;
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int err;
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unsigned int i, j, k;
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u_register_t mpidr;
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int cpuid;
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if (fdt_path_offset(dtb, "/cpus") >= 0) {
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return -EEXIST;
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}
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offs = fdt_add_subnode(dtb, 0, "cpus");
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if (offs < 0) {
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ERROR ("FDT: add subnode \"cpus\" node to parent node failed");
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return offs;
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}
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err = fdt_setprop_u32(dtb, offs, "#address-cells", 2);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"#address-cells", offs);
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return err;
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}
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err = fdt_setprop_u32(dtb, offs, "#size-cells", 0);
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if (err < 0) {
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ERROR ("FDT: write to \"%s\" property of node at offset %i failed\n",
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"#size-cells", offs);
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return err;
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}
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/*
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* Populate the node with the CPUs.
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* As libfdt prepends subnodes within a node, reverse the index count
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* so the CPU nodes would be better ordered.
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*/
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for (i = afflv2; i > 0U; i--) {
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for (j = afflv1; j > 0U; j--) {
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for (k = afflv0; k > 0U; k--) {
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mpidr = ((i - 1) << MPIDR_AFF2_SHIFT) |
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((j - 1) << MPIDR_AFF1_SHIFT) |
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((k - 1) << MPIDR_AFF0_SHIFT) |
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(read_mpidr_el1() & MPIDR_MT_MASK);
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cpuid = plat_core_pos_by_mpidr(mpidr);
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if (cpuid >= 0) {
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/* Valid MPID found */
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err = fdt_add_cpu(dtb, offs, mpidr);
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if (err < 0) {
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ERROR ("FDT: %s 0x%08x\n",
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"error adding CPU",
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(uint32_t)mpidr);
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return err;
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}
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}
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}
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}
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}
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return offs;
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}
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/**
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* fdt_adjust_gic_redist() - Adjust GICv3 redistributor size
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* @dtb: Pointer to the DT blob in memory
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* @nr_cores: Number of CPU cores on this system.
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* @gicr_frame_size: Size of the GICR frame per core
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*
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* On a GICv3 compatible interrupt controller, the redistributor provides
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* a number of 64k pages per each supported core. So with a dynamic topology,
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* this size cannot be known upfront and thus can't be hardcoded into the DTB.
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*
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* Find the DT node describing the GICv3 interrupt controller, and adjust
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* the size of the redistributor to match the number of actual cores on
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* this system.
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* A GICv4 compatible redistributor uses four 64K pages per core, whereas GICs
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* without support for direct injection of virtual interrupts use two 64K pages.
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* The @gicr_frame_size parameter should be 262144 and 131072, respectively.
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*
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* Return: 0 on success, negative error value otherwise.
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*/
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int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores,
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unsigned int gicr_frame_size)
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{
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int offset = fdt_node_offset_by_compatible(dtb, 0, "arm,gic-v3");
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uint64_t redist_size_64;
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uint32_t redist_size_32;
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void *val;
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int parent;
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int ac, sc;
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if (offset < 0) {
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return offset;
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}
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parent = fdt_parent_offset(dtb, offset);
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if (parent < 0) {
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return parent;
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}
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ac = fdt_address_cells(dtb, parent);
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sc = fdt_size_cells(dtb, parent);
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if (ac < 0 || sc < 0) {
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return -EINVAL;
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}
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if (sc == 1) {
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redist_size_32 = cpu_to_fdt32(nr_cores * gicr_frame_size);
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val = &redist_size_32;
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} else {
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redist_size_64 = cpu_to_fdt64(nr_cores *
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(uint64_t)gicr_frame_size);
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val = &redist_size_64;
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}
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/*
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* The redistributor is described in the second "reg" entry.
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* So we have to skip one address and one size cell, then another
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* address cell to get to the second size cell.
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*/
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return fdt_setprop_inplace_namelen_partial(dtb, offset, "reg", 3,
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(ac + sc + ac) * 4,
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val, sc * 4);
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}
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