772 lines
19 KiB
C
772 lines
19 KiB
C
/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "gpu_cmds.h"
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void
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gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
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{
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int ret;
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ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
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if (ret == 0)
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ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
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NULL, 0, 0, 0);
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igt_assert(ret == 0);
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}
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void
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gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
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{
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int ret;
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ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
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if (ret == 0)
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ret = drm_intel_gem_bo_context_exec(batch->bo, batch->ctx,
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batch_end, 0);
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igt_assert(ret == 0);
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}
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uint32_t
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gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
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uint8_t color)
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{
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uint8_t *curbe_buffer;
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uint32_t offset;
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curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
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sizeof(uint32_t) * 8,
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64);
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offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
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*curbe_buffer = color;
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return offset;
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}
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uint32_t
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gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
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{
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uint32_t *curbe_buffer;
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uint32_t offset;
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curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
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sizeof(uint32_t) * 8,
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64);
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offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
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*curbe_buffer++ = 0;
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*curbe_buffer = 1;
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return offset;
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}
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uint32_t
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gen7_fill_surface_state(struct intel_batchbuffer *batch,
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const struct igt_buf *buf,
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uint32_t format,
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int is_dst)
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{
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struct gen7_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
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offset = intel_batchbuffer_subdata_offset(batch, ss);
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ss->ss0.surface_type = SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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ss->ss1.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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intel_batchbuffer_subdata_offset(batch, ss) + 4,
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buf->bo, 0,
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read_domain, write_domain);
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igt_assert(ret == 0);
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ss->ss2.height = igt_buf_height(buf) - 1;
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ss->ss2.width = igt_buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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return offset;
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}
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uint32_t
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gen7_fill_binding_table(struct intel_batchbuffer *batch,
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const struct igt_buf *dst)
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{
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uint32_t *binding_table, offset;
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binding_table = intel_batchbuffer_subdata_alloc(batch, 32, 64);
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offset = intel_batchbuffer_subdata_offset(batch, binding_table);
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if (IS_GEN7(batch->devid))
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binding_table[0] = gen7_fill_surface_state(batch, dst,
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SURFACEFORMAT_R8_UNORM, 1);
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else
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binding_table[0] = gen8_fill_surface_state(batch, dst,
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SURFACEFORMAT_R8_UNORM, 1);
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return offset;
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}
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uint32_t
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gen11_fill_binding_table(struct intel_batchbuffer *batch,
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const struct igt_buf *src,const struct igt_buf *dst)
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{
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uint32_t *binding_table, offset;
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binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
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offset = intel_batchbuffer_subdata_offset(batch, binding_table);
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binding_table[0] = gen11_fill_surface_state(batch, src,
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SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
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0,0,
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0);
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binding_table[1] = gen11_fill_surface_state(batch, dst,
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SURFACE_BUFFER, SURFACEFORMAT_RAW,
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1,1,
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1);
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return offset;
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}
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uint32_t
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gen7_fill_kernel(struct intel_batchbuffer *batch,
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const uint32_t kernel[][4],
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size_t size)
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{
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uint32_t offset;
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offset = intel_batchbuffer_copy_data(batch, kernel, size, 64);
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return offset;
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}
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uint32_t
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gen7_fill_interface_descriptor(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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const uint32_t kernel[][4],
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size_t size)
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{
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struct gen7_interface_descriptor_data *idd;
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uint32_t offset;
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uint32_t binding_table_offset, kernel_offset;
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binding_table_offset = gen7_fill_binding_table(batch, dst);
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kernel_offset = gen7_fill_kernel(batch, kernel, size);
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idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
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offset = intel_batchbuffer_subdata_offset(batch, idd);
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idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
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idd->desc1.single_program_flow = 1;
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idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754;
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idd->desc2.sampler_count = 0; /* 0 samplers used */
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idd->desc2.sampler_state_pointer = 0;
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idd->desc3.binding_table_entry_count = 0;
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idd->desc3.binding_table_pointer = (binding_table_offset >> 5);
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idd->desc4.constant_urb_entry_read_offset = 0;
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idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */
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return offset;
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}
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void
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gen7_emit_state_base_address(struct intel_batchbuffer *batch)
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{
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OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
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/* general */
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OUT_BATCH(0);
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/* surface */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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BASE_ADDRESS_MODIFY);
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/* dynamic */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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BASE_ADDRESS_MODIFY);
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/* indirect */
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OUT_BATCH(0);
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/* instruction */
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OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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BASE_ADDRESS_MODIFY);
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/* general/dynamic/indirect/instruction access Bound */
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(0);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
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}
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void
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gen7_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads,
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uint32_t urb_entries, uint32_t urb_size,
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uint32_t curbe_size, uint32_t mode)
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{
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OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2));
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/* scratch buffer */
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OUT_BATCH(0);
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/* number of threads & urb entries */
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OUT_BATCH(threads << 16 |
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urb_entries << 8 |
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mode << 2); /* GPGPU vs media mode */
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OUT_BATCH(0);
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/* urb entry size & curbe size */
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OUT_BATCH(urb_size << 16 | /* in 256 bits unit */
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curbe_size); /* in 256 bits unit */
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/* scoreboard */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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void
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gen7_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
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{
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OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* curbe total data length */
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OUT_BATCH(64);
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/* curbe data start address, is relative to the dynamics base address */
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OUT_BATCH(curbe_buffer);
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}
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void
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gen7_emit_interface_descriptor_load(struct intel_batchbuffer *batch,
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uint32_t interface_descriptor)
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{
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OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
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OUT_BATCH(0);
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/* interface descriptor data length */
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if (IS_GEN7(batch->devid))
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OUT_BATCH(sizeof(struct gen7_interface_descriptor_data));
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else
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OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
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/* interface descriptor address, is relative to the dynamics base
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* address
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*/
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OUT_BATCH(interface_descriptor);
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}
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void
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gen7_emit_media_objects(struct intel_batchbuffer *batch,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height)
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{
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int i, j;
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for (i = 0; i < width / 16; i++) {
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for (j = 0; j < height / 16; j++) {
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gen_emit_media_object(batch, x + i * 16, y + j * 16);
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}
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}
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}
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void
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gen7_emit_gpgpu_walk(struct intel_batchbuffer *batch,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height)
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{
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uint32_t x_dim, y_dim, tmp, right_mask;
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/*
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* Simply do SIMD16 based dispatch, so every thread uses
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* SIMD16 channels.
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*
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* Define our own thread group size, e.g 16x1 for every group, then
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* will have 1 thread each group in SIMD16 dispatch. So thread
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* width/height/depth are all 1.
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*
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* Then thread group X = width / 16 (aligned to 16)
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* thread group Y = height;
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*/
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x_dim = (width + 15) / 16;
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y_dim = height;
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tmp = width & 15;
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if (tmp == 0)
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right_mask = (1 << 16) - 1;
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else
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right_mask = (1 << tmp) - 1;
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OUT_BATCH(GEN7_GPGPU_WALKER | 9);
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/* interface descriptor offset */
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OUT_BATCH(0);
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/* SIMD size, thread w/h/d */
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OUT_BATCH(1 << 30 | /* SIMD16 */
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0 << 16 | /* depth:1 */
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0 << 8 | /* height:1 */
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0); /* width:1 */
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/* thread group X */
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OUT_BATCH(0);
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OUT_BATCH(x_dim);
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/* thread group Y */
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OUT_BATCH(0);
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OUT_BATCH(y_dim);
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/* thread group Z */
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OUT_BATCH(0);
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OUT_BATCH(1);
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/* right mask */
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OUT_BATCH(right_mask);
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/* bottom mask, height 1, always 0xffffffff */
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OUT_BATCH(0xffffffff);
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}
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uint32_t
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gen8_spin_curbe_buffer_data(struct intel_batchbuffer *batch,
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uint32_t iters)
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{
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uint32_t *curbe_buffer;
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uint32_t offset;
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curbe_buffer = intel_batchbuffer_subdata_alloc(batch, 64, 64);
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offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
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*curbe_buffer = iters;
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return offset;
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}
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uint32_t
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gen8_fill_surface_state(struct intel_batchbuffer *batch,
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const struct igt_buf *buf,
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uint32_t format,
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int is_dst)
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{
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struct gen8_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
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offset = intel_batchbuffer_subdata_offset(batch, ss);
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ss->ss0.surface_type = SURFACE_2D;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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ss->ss0.vertical_alignment = 1; /* align 4 */
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ss->ss0.horizontal_alignment = 1; /* align 4 */
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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ss->ss8.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
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buf->bo, 0, read_domain, write_domain);
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igt_assert(ret == 0);
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ss->ss2.height = igt_buf_height(buf) - 1;
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ss->ss2.width = igt_buf_width(buf) - 1;
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ss->ss3.pitch = buf->stride - 1;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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return offset;
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}
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uint32_t
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gen11_fill_surface_state(struct intel_batchbuffer *batch,
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const struct igt_buf *buf,
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uint32_t surface_type,
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uint32_t format,
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uint32_t vertical_alignment,
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uint32_t horizontal_alignment,
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int is_dst)
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{
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struct gen8_surface_state *ss;
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uint32_t write_domain, read_domain, offset;
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int ret;
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if (is_dst) {
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write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
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} else {
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write_domain = 0;
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read_domain = I915_GEM_DOMAIN_SAMPLER;
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}
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ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
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offset = intel_batchbuffer_subdata_offset(batch, ss);
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ss->ss0.surface_type = surface_type;
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ss->ss0.surface_format = format;
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ss->ss0.render_cache_read_write = 1;
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ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
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ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
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if (buf->tiling == I915_TILING_X)
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ss->ss0.tiled_mode = 2;
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else if (buf->tiling == I915_TILING_Y)
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ss->ss0.tiled_mode = 3;
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else
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ss->ss0.tiled_mode = 0;
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ss->ss8.base_addr = buf->bo->offset;
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ret = drm_intel_bo_emit_reloc(batch->bo,
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intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
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buf->bo, 0, read_domain, write_domain);
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igt_assert(ret == 0);
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if (is_dst) {
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ss->ss1.memory_object_control = 2;
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ss->ss2.height = 1;
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ss->ss2.width = 95;
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ss->ss3.pitch = 0;
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ss->ss7.shader_chanel_select_r = 4;
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ss->ss7.shader_chanel_select_g = 5;
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ss->ss7.shader_chanel_select_b = 6;
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ss->ss7.shader_chanel_select_a = 7;
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}
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else {
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ss->ss1.qpitch = 4040;
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ss->ss1.base_mip_level = 31;
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ss->ss2.height = 9216;
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ss->ss2.width = 1019;
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ss->ss3.pitch = 64;
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ss->ss5.mip_count = 2;
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}
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return offset;
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}
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uint32_t
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gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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const uint32_t kernel[][4],
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size_t size)
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{
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struct gen8_interface_descriptor_data *idd;
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uint32_t offset;
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uint32_t binding_table_offset, kernel_offset;
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binding_table_offset = gen7_fill_binding_table(batch, dst);
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kernel_offset = gen7_fill_kernel(batch, kernel, size);
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idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
|
|
offset = intel_batchbuffer_subdata_offset(batch, idd);
|
|
|
|
idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
|
|
|
|
idd->desc2.single_program_flow = 1;
|
|
idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
|
|
|
|
idd->desc3.sampler_count = 0; /* 0 samplers used */
|
|
idd->desc3.sampler_state_pointer = 0;
|
|
|
|
idd->desc4.binding_table_entry_count = 0;
|
|
idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
|
|
|
|
idd->desc5.constant_urb_entry_read_offset = 0;
|
|
idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
|
|
|
|
idd->desc6.num_threads_in_tg = 1;
|
|
|
|
return offset;
|
|
}
|
|
|
|
uint32_t
|
|
gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
|
|
const struct igt_buf *src,const struct igt_buf *dst,
|
|
const uint32_t kernel[][4],
|
|
size_t size)
|
|
{
|
|
struct gen8_interface_descriptor_data *idd;
|
|
uint32_t offset;
|
|
uint32_t binding_table_offset, kernel_offset;
|
|
|
|
binding_table_offset = gen11_fill_binding_table(batch, src,dst);
|
|
kernel_offset = gen7_fill_kernel(batch, kernel, size);
|
|
|
|
idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
|
|
offset = intel_batchbuffer_subdata_offset(batch, idd);
|
|
|
|
idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
|
|
|
|
idd->desc2.single_program_flow = 1;
|
|
idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
|
|
|
|
idd->desc3.sampler_count = 0; /* 0 samplers used */
|
|
idd->desc3.sampler_state_pointer = 0;
|
|
|
|
idd->desc4.binding_table_entry_count = 0;
|
|
idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
|
|
|
|
idd->desc5.constant_urb_entry_read_offset = 0;
|
|
idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
|
|
|
|
idd->desc6.num_threads_in_tg = 1;
|
|
|
|
return offset;
|
|
}
|
|
|
|
void
|
|
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
|
|
|
|
/* general */
|
|
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
|
|
OUT_BATCH(0);
|
|
|
|
/* stateless data port */
|
|
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
|
|
|
|
/* surface */
|
|
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
|
|
|
|
/* dynamic */
|
|
OUT_RELOC(batch->bo,
|
|
I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
|
|
0, BASE_ADDRESS_MODIFY);
|
|
|
|
/* indirect */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
/* instruction */
|
|
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
|
|
BASE_ADDRESS_MODIFY);
|
|
|
|
/* general state buffer size */
|
|
OUT_BATCH(0xfffff000 | 1);
|
|
/* dynamic state buffer size */
|
|
OUT_BATCH(1 << 12 | 1);
|
|
/* indirect object buffer size */
|
|
OUT_BATCH(0xfffff000 | 1);
|
|
/* instruction buffer size, must set modify enable bit, otherwise it may
|
|
* result in GPU hang
|
|
*/
|
|
OUT_BATCH(1 << 12 | 1);
|
|
}
|
|
|
|
void
|
|
gen8_emit_media_state_flush(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2));
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
void
|
|
gen8_emit_vfe_state(struct intel_batchbuffer *batch, uint32_t threads,
|
|
uint32_t urb_entries, uint32_t urb_size,
|
|
uint32_t curbe_size)
|
|
{
|
|
OUT_BATCH(GEN7_MEDIA_VFE_STATE | (9 - 2));
|
|
|
|
/* scratch buffer */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
/* number of threads & urb entries */
|
|
OUT_BATCH(threads << 16 |
|
|
urb_entries << 8);
|
|
|
|
OUT_BATCH(0);
|
|
|
|
/* urb entry size & curbe size */
|
|
OUT_BATCH(urb_size << 16 |
|
|
curbe_size);
|
|
|
|
/* scoreboard */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
}
|
|
|
|
void
|
|
gen8_emit_gpgpu_walk(struct intel_batchbuffer *batch,
|
|
unsigned int x, unsigned int y,
|
|
unsigned int width, unsigned int height)
|
|
{
|
|
uint32_t x_dim, y_dim, tmp, right_mask;
|
|
|
|
/*
|
|
* Simply do SIMD16 based dispatch, so every thread uses
|
|
* SIMD16 channels.
|
|
*
|
|
* Define our own thread group size, e.g 16x1 for every group, then
|
|
* will have 1 thread each group in SIMD16 dispatch. So thread
|
|
* width/height/depth are all 1.
|
|
*
|
|
* Then thread group X = width / 16 (aligned to 16)
|
|
* thread group Y = height;
|
|
*/
|
|
x_dim = (width + 15) / 16;
|
|
y_dim = height;
|
|
|
|
tmp = width & 15;
|
|
if (tmp == 0)
|
|
right_mask = (1 << 16) - 1;
|
|
else
|
|
right_mask = (1 << tmp) - 1;
|
|
|
|
OUT_BATCH(GEN7_GPGPU_WALKER | 13);
|
|
|
|
OUT_BATCH(0); /* kernel offset */
|
|
OUT_BATCH(0); /* indirect data length */
|
|
OUT_BATCH(0); /* indirect data offset */
|
|
|
|
/* SIMD size, thread w/h/d */
|
|
OUT_BATCH(1 << 30 | /* SIMD16 */
|
|
0 << 16 | /* depth:1 */
|
|
0 << 8 | /* height:1 */
|
|
0); /* width:1 */
|
|
|
|
/* thread group X */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(x_dim);
|
|
|
|
/* thread group Y */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(y_dim);
|
|
|
|
/* thread group Z */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(1);
|
|
|
|
/* right mask */
|
|
OUT_BATCH(right_mask);
|
|
|
|
/* bottom mask, height 1, always 0xffffffff */
|
|
OUT_BATCH(0xffffffff);
|
|
}
|
|
|
|
void
|
|
gen_emit_media_object(struct intel_batchbuffer *batch,
|
|
unsigned int xoffset, unsigned int yoffset)
|
|
{
|
|
OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2));
|
|
|
|
/* interface descriptor offset */
|
|
OUT_BATCH(0);
|
|
|
|
/* without indirect data */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
/* scoreboard */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
/* inline data (xoffset, yoffset) */
|
|
OUT_BATCH(xoffset);
|
|
OUT_BATCH(yoffset);
|
|
if (AT_LEAST_GEN(batch->devid, 8) && !IS_CHERRYVIEW(batch->devid))
|
|
gen8_emit_media_state_flush(batch);
|
|
}
|
|
|
|
void
|
|
gen9_emit_state_base_address(struct intel_batchbuffer *batch)
|
|
{
|
|
OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2));
|
|
|
|
/* general */
|
|
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
|
|
OUT_BATCH(0);
|
|
|
|
/* stateless data port */
|
|
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
|
|
|
|
/* surface */
|
|
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
|
|
|
|
/* dynamic */
|
|
OUT_RELOC(batch->bo,
|
|
I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
|
|
0, BASE_ADDRESS_MODIFY);
|
|
|
|
/* indirect */
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0);
|
|
|
|
/* instruction */
|
|
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
|
|
BASE_ADDRESS_MODIFY);
|
|
|
|
/* general state buffer size */
|
|
OUT_BATCH(0xfffff000 | 1);
|
|
/* dynamic state buffer size */
|
|
OUT_BATCH(1 << 12 | 1);
|
|
/* indirect object buffer size */
|
|
OUT_BATCH(0xfffff000 | 1);
|
|
/* intruction buffer size, must set modify enable bit, otherwise it may
|
|
* result in GPU hang
|
|
*/
|
|
OUT_BATCH(1 << 12 | 1);
|
|
|
|
/* Bindless surface state base address */
|
|
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
|
|
OUT_BATCH(0);
|
|
OUT_BATCH(0xfffff000);
|
|
}
|